From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HNIdN-0000LZ-Nk for qemu-devel@nongnu.org; Fri, 02 Mar 2007 20:02:01 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HNIdN-0000L4-8d for qemu-devel@nongnu.org; Fri, 02 Mar 2007 20:02:01 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HNIdN-0000L1-3S for qemu-devel@nongnu.org; Fri, 02 Mar 2007 20:02:01 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1HNIdM-0005CR-E2 for qemu-devel@nongnu.org; Fri, 02 Mar 2007 20:02:00 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] pcnet32 driver change, please test Date: Sat, 3 Mar 2007 01:01:55 +0000 References: <20070302200949.GD27636@networkno.de> <20070302231450.GA6741@miranda.arrow> <20070302.175333.1622572844.imp@bsdimp.com> In-Reply-To: <20070302.175333.1622572844.imp@bsdimp.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200703030101.56126.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > : I find this curious... C99 (6.7.2.1) says "the allocation order of > : bit-fields within a unit (high-order to low-order or low-order to > : high-order) is implementation defined". I can't see any requirement > : for this, so is it just convention that bitfields on big endian systems > : start from the most significant bit, and those on little endian systems > : start from the least significant bit? (My thinking is that endianness > : usually refers to byte ordering and not so much bit ordering.) > > This is a convention that goes back a very long ways. It was this way > in the mid 1980's, and has remained true through today. I've > personally observed this to be the case on many different MIPS > compilers, ARM compilers and SPARC compilers over the years. I'm fairly sure I've seen targets that use other bitfield orderings, though I can't remember offhand what they were. Paul