From: Julian Seward <jseward@acm.org>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] SSE 'maxps' instruction bug?
Date: Tue, 13 Mar 2007 14:03:06 +0000 [thread overview]
Message-ID: <200703131403.06378.jseward@acm.org> (raw)
In-Reply-To: <Pine.LNX.4.64.0703121921580.14408@linmac.oyster.ru>
> QEMU and Core 2 Duo disagree on the handling of NaNs it seems.
>
> http://courses.ece.uiuc.edu/ece390/books/labmanual/inst-ref-simd.html
> - this implies that MAXPS should leave the NaNs alone, no idea how
> normative that is though (and no IA32 manual at hand)
Having looked at an IA32 manual I'd say the inst-ref-simd.html
description agrees with it, so the Core 2 behaviour is what
qemu should do.
J
next prev parent reply other threads:[~2007-03-13 14:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-03-12 14:50 [Qemu-devel] SSE 'maxps' instruction bug? Julian Seward
2007-03-12 16:27 ` malc
2007-03-13 14:03 ` Julian Seward [this message]
2007-03-13 23:07 ` Tim Olson
2007-03-14 2:21 ` Julian Seward
2007-03-16 18:07 ` Rob Landley
2007-03-16 18:10 ` Julian Seward
2007-03-16 20:17 ` Rob Landley
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