Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction

[Stuart Brady <sdbrady@ntlworld.com>]

On Sun, Mar 25, 2007 at 03:43:16AM +0200, Aurelien Jarno wrote:
> Thiemo Seufer a écrit :
[...]
> >  - Execute the second branch's delay slot instruction. Increment PC.
[...]

I'm surprised that this step would be there -- I would have expected it
to be simpler to execute the target of the first branch in place of the
second branch's delay slot.

> Yep I confirm that, it is clearly explained starting at the page 54 of
> the SPARC v8 manual. To avoid this behaviour it is possible to cancel
> the delay slot instruction by having a=1.

SPARC doesn't have the "execute the second branch's delay slot" step.

>From the table on page 56, it seems to execute:

    branch1
    branch2
    target of branch1 (one instruction only)
    target of branch2 (continuing)

PA-RISC has the same requirement (PA-RISC 2.0 manual, pages 4-5 and 4-6,
and PA-RISC 1.1 manual, page 4-10).
-- 
Stuart Brady