Re: IRQ handling (was [Qemu-devel] qemu Makefile.target vl.h hw/acpi.c hw/adlib.c ...)

[Jamie Lokier <jamie@shareable.org>]

J. Mayer wrote:
> > No. Since MIPS{32,64}R2 the CP0 is standardized and a mandatory part of
> > a MIPS compatible CPU.
> 
> Yes, I know MIPS want always CP0 to be present. I should have put a
> smiley somewhere. I wanted just to point the fact that the CPU itself
> does not need the CP0 controller to run and that one could easily
> imagine designing a core without the CP0 controller.

I just want to say I have programmed a MIPS-ish core which did not
have a CP0 controller.  It was the Alteon AceNIC gigabit ethernet
controller, and it had two CPU cores implementing the MIPS integer
instruction set.  We used the standard mips-elf GCC to compile for it.

I'm under the impression that copying the basic MIPS instruction set
is not uncommon for the odd ASIC here and there, as it doesn't bump
into the licensing problems that copying ARM instructions does, and
it's quite simple.

-- Jamie