From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HbfNV-00085j-NE for qemu-devel@nongnu.org; Wed, 11 Apr 2007 12:09:01 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HbfNS-000845-Jq for qemu-devel@nongnu.org; Wed, 11 Apr 2007 12:09:00 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HbfNS-00083x-A4 for qemu-devel@nongnu.org; Wed, 11 Apr 2007 12:08:58 -0400 Received: from phoenix.bawue.net ([193.7.176.60] helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HbfJN-0003C6-NW for qemu-devel@nongnu.org; Wed, 11 Apr 2007 12:04:46 -0400 Date: Wed, 11 Apr 2007 17:05:16 +0100 Subject: Re: [Qemu-devel] Re: Detecting an assembly instruction in QEMU Message-ID: <20070411160515.GA31609@networkno.de> References: <83a4d4ca0704060515l172d6f9ep59b6467c6e49f250@mail.gmail.com> <83a4d4ca0704080713t596e4d83lbd1c495d92eda581@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Atif Hashmi Cc: qemu-devel@nongnu.org Atif Hashmi wrote: > Hi Eduardo, > > Thanks a lot for your help. I really appreciate it. I have added the > functionality that I wanted. Just in case it might help somebody reading this list, I use the appended patch to detect a special instruction pattern as pass/fail condition and shut down qemu with the appropriate message. Thiemo Index: qemu-cvs/target-mips/exec.h =================================================================== --- qemu-cvs.orig/target-mips/exec.h +++ qemu-cvs/target-mips/exec.h @@ -140,6 +140,9 @@ uint64_t do_sdr_kernel (uint64_t); #endif #endif +void do_avp_ok (void); +void do_avp_fail (void); + void do_pmon (int function); void dump_sc (void); Index: qemu-cvs/target-mips/op.c =================================================================== --- qemu-cvs.orig/target-mips/op.c +++ qemu-cvs/target-mips/op.c @@ -954,6 +954,16 @@ OP_COND(lez, (int32_t)T0 <= 0); OP_COND(ltz, (int32_t)T0 < 0); +// +void op_avp_ok (void) { + CALL_FROM_TB0(do_avp_ok); + RETURN(); +} +void op_avp_fail (void) { + CALL_FROM_TB0(do_avp_fail); + RETURN(); +} + /* Branches */ //#undef USE_DIRECT_JUMP Index: qemu-cvs/target-mips/op_helper.c =================================================================== --- qemu-cvs.orig/target-mips/op_helper.c +++ qemu-cvs/target-mips/op_helper.c @@ -535,6 +535,18 @@ fputs("\n", logfile); } +void do_avp_ok (void) +{ + puts("ok"); + qemu_system_shutdown_request(); +} + +void do_avp_fail (void) +{ + puts("fail"); + qemu_system_shutdown_request(); +} + void do_pmon (int function) { function /= 2; Index: qemu-cvs/target-mips/translate.c =================================================================== --- qemu-cvs.orig/target-mips/translate.c +++ qemu-cvs/target-mips/translate.c @@ -881,6 +881,14 @@ uint32_t uimm; const char *opn = "unk"; +if (opc == OPC_SLTIU && rs == 0 && rt == 0 && (((uint16_t)imm == 0xabc2) | ((uint16_t)imm == 0xabc1))) { + if ((uint16_t)imm == 0xabc2) + gen_op_avp_ok(); + else + gen_op_avp_fail(); + ctx->bstate = BS_STOP; + return; +} if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { /* if no destination, treat it as a NOP * For addi, we must generate the overflow exception when needed.