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Date: Wed, 9 May 2007 16:26:02 +0100
Subject: Re: [Qemu-devel] [PATCH, RFC] Fix softfloat NaN handling
Message-ID: <20070509152602.GB29867@networkno.de>
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From: Thiemo Seufer <ths@networkno.de>
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To: Blue Swirl <blauwirbel@gmail.com>
Cc: qemu-devel@nongnu.org

Blue Swirl wrote:
> On 5/9/07, Thiemo Seufer <ths@networkno.de> wrote:
> >Hello All,
> >
> >The relevant IEEE standards don't define if a set or a clear bit is
> >used to distinguish between QNaN and SNaN. MIPS, and apparently
> >PA RISC, made a different choice than the rest of the industry.
> 
> On Sparc, the rule is as follows:
> 
> SNaN: sign undefined,  exponent 255, mantissa  0xxx...and at least one
> bit must be nonzero
> QNaN: sign undefined, exponent 255,  mantissa 1xxx...
> 
> Is this the same as MIPS?

For MIPS, and allegedly HPPA, the meaning of the highest bit in the
mantissa is inverted. IOW, 0xxx... is a QNaN, 1xxx... is a SNaN.
The rest is the same, and AFAIK mandated by the standard.


Thiemo