From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HvZQU-0003qE-3f for qemu-devel@nongnu.org; Tue, 05 Jun 2007 09:50:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HvZQS-0003pY-C8 for qemu-devel@nongnu.org; Tue, 05 Jun 2007 09:50:21 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HvZQS-0003pT-8j for qemu-devel@nongnu.org; Tue, 05 Jun 2007 09:50:20 -0400 Received: from phoenix.bawue.net ([193.7.176.60] helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HvZQR-0001yy-SD for qemu-devel@nongnu.org; Tue, 05 Jun 2007 09:50:20 -0400 Date: Tue, 5 Jun 2007 14:50:17 +0100 Subject: Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values Message-ID: <20070605135017.GA18315@networkno.de> References: <20070604213747.GA8768@farad.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070604213747.GA8768@farad.aurel32.net> From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org Aurelien Jarno wrote: > Hi all, > > The patch below fixes the Status_rw_bitmask values for 64-bit CPUs: > - Reverse endianess is currently not implemented, the RE bit should > not be writable. OTOH, those CPUs support RE, that's why I left the bit writable. I think you'll have to boot RiscOS to check the difference, I don't know of any other user. :-) > - 64-bit is implemented, the PX bit should be writable. The current version is correct, R4000 and 5K don't implement PX, the 20Kc and later CPUs do. Thiemo