From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1I366d-0000tR-Rz for qemu-devel@nongnu.org; Tue, 26 Jun 2007 04:08:59 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1I366c-0000tF-DM for qemu-devel@nongnu.org; Tue, 26 Jun 2007 04:08:59 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1I366c-0000tC-A8 for qemu-devel@nongnu.org; Tue, 26 Jun 2007 04:08:58 -0400 Received: from phoenix.bawue.net ([193.7.176.60] helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1I366b-0005sq-TD for qemu-devel@nongnu.org; Tue, 26 Jun 2007 04:08:58 -0400 Date: Tue, 26 Jun 2007 09:00:36 +0100 Subject: Re: [Qemu-devel] [PATCH, RFC] More than 2G of memory on 64-bit hosts Message-ID: <20070626080036.GE3665@networkno.de> References: <200706252226.50773.michal.schulz@gmx.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Karl Magdsick Cc: qemu-devel@nongnu.org Karl Magdsick wrote: [snip] > With proper support from the compiler, it's theoretically possible on > x86-64 systems to use 32-bit pointers in long mode (16 general purpose > 64-bit registers). (There's an instruction prefix that will cause the > CPU to perform 32-bit pointer calculations in the 64-bit address > space.) I'm not aware of any systems that use this, however. (Getting > the speed boost from fewer register spills while not paying the space > cost of 64-bit pointers sounds very attractive in many applications, > though.) FYI, the MIPS N32 ABI does that (64bit wide registers, 32bit address space, data type sizes compatible to pure 32bit programs). Thiemo