From: Paul Walmsley <paul@pwsan.com>
To: linux-omap-open-source@linux.omap.com
Subject: [PATCH 05/22] omap2 clock: fix CodingStyle issues
Date: Thu, 02 Aug 2007 12:10:07 -0600 [thread overview]
Message-ID: <20070802181141.896203830@pwsan.com> (raw)
In-Reply-To: 20070802181002.792550043@pwsan.com
[-- Attachment #1: codingstyle-clock.c.patch --]
[-- Type: text/plain, Size: 3899 bytes --]
Clean up some CodingStyle non-conformances in clock.c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -396,7 +396,7 @@ static inline u32 omap2_divider_from_tab
if (div_array == NULL)
return ~1;
- for (i=0; i < size; i++) {
+ for (i = 0; i < size; i++) {
test_rate = src_rate / *div_array;
if (test_rate <= tgt_rate)
return *div_array;
@@ -418,45 +418,45 @@ static u32 omap2_clksel_round_rate(struc
u32 gfx_div[] = {2, 3, 4};
u32 sysclkout_div[] = {1, 2, 4, 8, 16};
u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
- u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
+ u32 vlynq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
u32 best_div = ~0, asize = 0;
u32 *div_array = NULL;
switch (tclk->flags & SRC_RATE_SEL_MASK) {
case CM_GFX_SEL1:
- asize = 3;
+ asize = ARRAY_SIZE(gfx_div);
div_array = gfx_div;
break;
case CM_PLL_SEL1:
return omap2_dpll_round_rate(target_rate);
case CM_SYSCLKOUT_SEL1:
- asize = 5;
+ asize = ARRAY_SIZE(sysclkout_div);
div_array = sysclkout_div;
break;
case CM_CORE_SEL1:
- if(tclk == &dss1_fck){
- if(tclk->parent == &core_ck){
- asize = 10;
+ if (tclk == &dss1_fck) {
+ if (tclk->parent == &core_ck) {
+ asize = ARRAY_SIZE(dss1_div);
div_array = dss1_div;
} else {
*new_div = 0; /* fixed clk */
return(tclk->parent->rate);
}
- } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
- if(tclk->parent == &core_ck){
- asize = 10;
- div_array = vylnq_div;
+ } else if ((tclk == &vlynq_fck) && cpu_is_omap2420()) {
+ if (tclk->parent == &core_ck) {
+ asize = ARRAY_SIZE(vlynq_div);
+ div_array = vlynq_div;
} else {
*new_div = 0; /* fixed clk */
- return(tclk->parent->rate);
+ return (tclk->parent->rate);
}
}
break;
}
best_div = omap2_divider_from_table(asize, div_array,
- tclk->parent->rate, target_rate);
- if (best_div == ~0){
+ tclk->parent->rate, target_rate);
+ if (best_div == ~0) {
*new_div = 1;
return best_div; /* signal error */
}
@@ -778,7 +778,6 @@ static u32 omap2_clksel_get_divisor(stru
/* Set the clock rate for a clock source */
static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
{
int ret = -EINVAL;
void __iomem * reg;
@@ -795,7 +794,7 @@ static int omap2_clk_set_rate(struct clk
validrate = omap2_clksel_round_rate(clk, rate, &new_div);
if (validrate != rate)
- return(ret);
+ return ret;
field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
if (div_sel == 0)
@@ -837,8 +836,9 @@ static int omap2_clk_set_rate(struct clk
wmb();
}
ret = 0;
- } else if (clk->set_rate != 0)
+ } else if (clk->set_rate != 0) {
ret = clk->set_rate(clk, rate);
+ }
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
propagate_rate(clk);
@@ -872,10 +872,10 @@ static u32 omap2_get_src_field(u32 *type
else if (src_clk == &core_ck) /* divided clock */
val = 0x10; /* rate needs fixing */
} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
- cpu_is_omap2420()){
+ cpu_is_omap2420()) {
mask = OMAP2420_CLKSEL_VLYNQ_MASK;
mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
- if(src_clk == &func_96m_ck)
+ if (src_clk == &func_96m_ck)
val = 0;
else if (src_clk == &core_ck)
val = 0x10;
@@ -1034,7 +1034,7 @@ static int omap2_select_table_rate(struc
if (!found_speed) {
printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
- rate / 1000000);
+ rate / 1000000);
return -EINVAL;
}
--
next prev parent reply other threads:[~2007-08-02 18:10 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-08-02 18:10 [PATCH 00/22] omap2 clock: Bugfixes and cleanups in OMAP2 clock framework Paul Walmsley
2007-08-02 18:10 ` [PATCH 01/22] omap2 clock: drop meaningless RATE_CKCTLs Paul Walmsley
2007-08-02 18:10 ` [PATCH 02/22] omap2 clock: fix incorrect rate calculation for osc_ck, sys_ck Paul Walmsley
2007-08-10 21:08 ` [PATCH 02/22 - Reverse] omap2 osc & sys clock calculation Woodruff, Richard
2007-08-13 7:03 ` Tony Lindgren
2007-08-02 18:10 ` [PATCH 03/22] omap2 clock: fix clksel divisor bug Paul Walmsley
2007-08-02 18:10 ` [PATCH 04/22] omap2 clock: vlynq_fck recalc should be clksel, not followparent Paul Walmsley
2007-08-02 18:10 ` Paul Walmsley [this message]
2007-08-02 18:10 ` [PATCH 06/22] omap2 clock: drop unnecessary variable in omap2_clk_round_rate() Paul Walmsley
2007-08-02 18:10 ` [PATCH 07/22] omap2 clock: get rid of sleep_ck Paul Walmsley
2007-08-02 18:10 ` [PATCH 08/22] omap2 clock: clean up dss2_fck clock flags Paul Walmsley
2007-08-02 18:10 ` [PATCH 09/22] omap2 clock: move SDRC-related code from clock.c to memory.c Paul Walmsley
2007-08-02 18:10 ` [PATCH 10/22] omap2 clock: use symbolic constants in clock.h rate_offset/src_offset fields Paul Walmsley
2007-08-02 18:10 ` [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked as present on OMAP2430 Paul Walmsley
2007-08-02 18:45 ` [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent " Woodruff, Richard
2007-08-02 19:05 ` Woodruff, Richard
2007-08-03 18:09 ` Paul Walmsley
2007-08-03 18:47 ` Woodruff, Richard
2007-08-04 15:56 ` Paul Walmsley
2007-08-04 22:02 ` Woodruff, Richard
2007-08-10 9:43 ` Tony Lindgren
2007-08-02 18:10 ` [PATCH 12/22] omap2 clock: vlynq_fck is missing clksel divider code Paul Walmsley
2007-08-02 18:10 ` [PATCH 13/22] omap2 clock: convert PARENT_CONTROLS_CLOCK into a clock flag Paul Walmsley
2007-08-02 18:10 ` [PATCH 14/22] omap2 clock: omap2 clock.c: Consolidate wait-for-lock code Paul Walmsley
2007-08-02 18:10 ` [PATCH 15/22] omap2 clock: return -EINVAL if no clock enable code; fix dpll_ck enable Paul Walmsley
2007-08-02 18:10 ` [PATCH 16/22] omap2 clock: From: Paul Walmsley <paul@pwsan.com> Subject: Paul Walmsley
2007-08-02 18:10 ` [PATCH 17/22] omap2 clock: Cleanup in clksel-related code; add sys_clkout2 divisor handling Paul Walmsley
2007-08-02 18:10 ` [PATCH 18/22] omap2 clock: Use symbolic constants in clock.c Paul Walmsley
2007-08-02 18:10 ` [PATCH 19/22] omap2 clock: use dedicated omap2_dpll_recalc() for DPLL recalc func Paul Walmsley
2007-08-02 18:10 ` [PATCH 20/22] omap2 clock: add fixed divisor clock code Paul Walmsley
2007-08-02 18:10 ` [PATCH 21/22] omap2 clock: remove fixed rate from mdm_osc_ck Paul Walmsley
2007-08-02 18:10 ` [PATCH 22/22] omap2 clock: get rid of omap2_followparent_recalc() Paul Walmsley
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