From: Ralf Baechle <ralf@linux-mips.org>
To: Mohamed Bamakhrama <bamakhrama@gmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Context switches & interrupts affecting cache?
Date: Fri, 3 Aug 2007 13:40:23 +0100 [thread overview]
Message-ID: <20070803124023.GA16519@linux-mips.org> (raw)
In-Reply-To: <40378e40708030359h3729e4b1m5390c258b29d6ae0@mail.gmail.com>
On Fri, Aug 03, 2007 at 12:59:41PM +0200, Mohamed Bamakhrama wrote:
> Hi all,
> I have one question regarding context switches between user and kernel
> modes and interrupts. Do they invalidate the I-cache or D-cache?
Never on MIPS.
I call an architecture that would require a cacheflush for such a
context switch totally broken and yes, they exist - but nothing from
the MIPS family.
Ralf
next prev parent reply other threads:[~2007-08-03 12:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-08-03 10:59 Context switches & interrupts affecting cache? Mohamed Bamakhrama
2007-08-03 12:40 ` Ralf Baechle [this message]
2007-08-03 12:51 ` Mohamed Bamakhrama
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