From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Christoph Egger" Subject: [PATCH] 1/3: MCA/MCE correctable error handling Date: Tue, 21 Aug 2007 15:31:32 +0200 Message-ID: <200708211531.32552.Christoph.Egger@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="Boundary-00=_0kuyGimRfhzY3XV" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com Cc: Gavin.Maltby@sun.com, Keir Fraser List-Id: xen-devel@lists.xenproject.org --Boundary-00=_0kuyGimRfhzY3XV Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline This is patch 1/3. Signed-off-by: Christoph Egger =2D-=20 AMD Saxony, Dresden, Germany Operating System Research Center Legal Information: AMD Saxony Limited Liability Company & Co. KG Sitz (Gesch=E4ftsanschrift): Wilschdorfer Landstr. 101, 01109 Dresden, Deutschland Registergericht Dresden: HRA 4896 vertretungsberechtigter Komplement=E4r: AMD Saxony LLC (Sitz Wilmington, Delaware, USA) Gesch=E4ftsf=FChrer der AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy --Boundary-00=_0kuyGimRfhzY3XV Content-Type: text/x-diff; charset=us-ascii; name=mca_diff1_cleanup.diff Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=mca_diff1_cleanup.diff diff -r 256160ff19b7 xen/arch/x86/cpu/mcheck/mce.c --- a/xen/arch/x86/cpu/mcheck/mce.c Thu Aug 16 13:27:59 2007 +0100 +++ b/xen/arch/x86/cpu/mcheck/mce.c Thu Aug 16 16:34:45 2007 +0000 @@ -15,7 +15,7 @@ #include "mce.h" int mce_disabled = 0; -int nr_mce_banks; +unsigned int nr_mce_banks; /* Handle unconfigured int18 (should never happen) */ static fastcall void unexpected_machine_check(struct cpu_user_regs * regs, long error_code) @@ -29,35 +29,49 @@ void fastcall (*machine_check_vector)(st /* This has to be run for each processor */ void mcheck_init(struct cpuinfo_x86 *c) { - if (mce_disabled==1) + uint32_t mca, mce; + + if (mce_disabled == 1) { + printk("MCE support disabled by bootparam\n"); return; + } + + /* Xen requires an i686 class CPU. So this + * check should be almost always true here. */ + mca = cpu_has(c, X86_FEATURE_MCA); + mce = cpu_has(c, X86_FEATURE_MCE); + + if (!mca && !mce) { + printk(KERN_INFO "CPU%i: No machine check support available\n", + smp_processor_id()); + return; + } switch (c->x86_vendor) { - case X86_VENDOR_AMD: - if (c->x86==6 || c->x86==15) - amd_mcheck_init(c); - break; + case X86_VENDOR_AMD: + amd_mcheck_init(c); + break; - case X86_VENDOR_INTEL: + case X86_VENDOR_INTEL: #ifndef CONFIG_X86_64 - if (c->x86==5) - intel_p5_mcheck_init(c); - if (c->x86==6) - intel_p6_mcheck_init(c); + if (c->x86==5) + intel_p5_mcheck_init(c); + if (c->x86==6) + intel_p6_mcheck_init(c); #endif - if (c->x86==15) - intel_p4_mcheck_init(c); - break; + if (c->x86==15) + intel_p4_mcheck_init(c); + break; #ifndef CONFIG_X86_64 - case X86_VENDOR_CENTAUR: - if (c->x86==5) - winchip_mcheck_init(c); - break; + case X86_VENDOR_CENTAUR: + if (c->x86==5) + winchip_mcheck_init(c); + break; #endif - default: - break; + default: + break; } } diff -r 256160ff19b7 xen/arch/x86/cpu/mcheck/mce.h --- a/xen/arch/x86/cpu/mcheck/mce.h Thu Aug 16 13:27:59 2007 +0100 +++ b/xen/arch/x86/cpu/mcheck/mce.h Thu Aug 16 16:34:45 2007 +0000 @@ -10,5 +10,4 @@ extern fastcall void (*machine_check_vec extern fastcall void (*machine_check_vector)(struct cpu_user_regs *, long error_code); extern int mce_disabled __initdata; -extern int nr_mce_banks; - +extern unsigned int nr_mce_banks; --Boundary-00=_0kuyGimRfhzY3XV Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --Boundary-00=_0kuyGimRfhzY3XV--