From: Dave Jones <davej@redhat.com>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Nick Piggin <npiggin@suse.de>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Andi Kleen <ak@suse.de>
Subject: Re: [patch] x86: improved memory barrier implementation
Date: Sat, 29 Sep 2007 21:43:14 -0400 [thread overview]
Message-ID: <20070930014314.GA12669@redhat.com> (raw)
In-Reply-To: <20070928170719.2f617a7a@the-village.bc.nu>
On Fri, Sep 28, 2007 at 05:07:19PM +0100, Alan Cox wrote:
> > Winchip: can any of these CPUs with ooostores do SMP? If not, then smp_wmb
> > can also be a simple barrier on i386 too.
>
> The IDT Winchip can do SMP apparently.
>From the Winchip3 (which was the final winchip) specs..
"The IDT WinChip 3 processor also omits the software interface
to the Intel-proprietary symmetric multiprocessing support: APIC.
This bus function is omitted since the target market for the
IDT WinChip 3 processor is typical desktop systems (which
do not support APIC multiprocessing)."
It didn't offer any alternative DIY-SMP either (or at least
none that's documented).
Centaur only became SMP capable with some of the C3 Nehemiah's
a year or two back.
Dave
--
http://www.codemonkey.org.uk
prev parent reply other threads:[~2007-09-30 1:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-28 15:48 [patch] x86: improved memory barrier implementation Nick Piggin
2007-09-28 16:07 ` Alan Cox
2007-09-28 16:15 ` Linus Torvalds
2007-09-29 13:17 ` Nick Piggin
2007-09-29 16:07 ` Linus Torvalds
2007-09-30 12:16 ` Nick Piggin
2007-09-28 16:54 ` Nick Piggin
2007-09-28 17:18 ` Alan Cox
2007-09-29 13:19 ` Nick Piggin
2007-09-30 1:43 ` Dave Jones [this message]
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