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Date:	Mon, 1 Oct 2007 11:24:33 +0100
From:	Ralf Baechle <ralf@linux-mips.org>
To:	David Daney <ddaney@avtrex.com>
Cc:	Fuxin Zhang <fxzhang@ict.ac.cn>, linux-mips@linux-mips.org
Subject: Re: cmpxchg broken in some situation
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On Sun, Sep 30, 2007 at 08:59:07PM -0700, David Daney wrote:

> David Daney wrote:
> >Ralf Baechle wrote:
> >>+    } else if (cpu_has_llsc) {                    \
> >>+        __asm__ __volatile__(                    \
> >>+        "    .set    push                \n"    \
> >>+        "    .set    noat                \n"    \
> >>+        "    .set    mips3                \n"    \
> >>+        "1:    " ld "    %0, %2        # __cmpxchg_u32    \n"    \
> >>+        "    bne    %0, %z3, 2f            \n"    \
> >>+        "    .set    mips0                \n"    \
> >>+        "    move    $1, %z4                \n"    \
> >>+        "    .set    mips3                \n"    \
> >>+        "    " st "    $1, %1                \n"    \
> >>+        "    beqz    $1, 3f                \n"    \
> >>+        "2:                        \n"    \
> >>+        "    .subsection 2                \n"    \
> >>+        "3:    b    1b                \n"    \
> >>+        "    .previous                \n"    \
> >>+        "    .set    pop                \n"    \
> >>+        : "=&r" (__ret), "=R" (*m)                \
> >>+        : "R" (*m), "Jr" (old), "Jr" (new)            \
> >>+        : "memory");                        \
> >>  
> >Is a 'sync' needed after the 'sc'?
> >
> >According to this message:
> >http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20070919084515.GM9972%40networkno.de 
> >
> >it would seem so.
> 
> Drat, I probably posted too soon.  That is the smp_llsc_mb(); isn't it.

Yes - and the answer to your original question is a clear and definate
maybe ;-)

In the kernel we can afford to optimize for every piece of silicon on earth.
In userspace we can't make that sort of compile time choices as easily so
it's a better idea to just litter a few SYNCs over the code.

  Ralf