From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IgR3s-0002tB-6K for qemu-devel@nongnu.org; Fri, 12 Oct 2007 16:24:44 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IgR3r-0002sJ-9I for qemu-devel@nongnu.org; Fri, 12 Oct 2007 16:24:43 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IgR3r-0002s4-1r for qemu-devel@nongnu.org; Fri, 12 Oct 2007 16:24:43 -0400 Received: from relay01.mx.bawue.net ([193.7.176.67]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IgR3q-00078V-K5 for qemu-devel@nongnu.org; Fri, 12 Oct 2007 16:24:42 -0400 Date: Fri, 12 Oct 2007 21:24:08 +0100 From: Thiemo Seufer Subject: Re: [Qemu-devel] RFC: fix run of 32 bits Linux executables on 64 bits targets Message-ID: <20071012202408.GM3379@networkno.de> References: <1192002128.9976.186.camel@rapid> <470C8AD9.6000002@bellard.org> <20071010174906.GC3379@networkno.de> <470D1C9A.2000505@bellard.org> <1192140040.9976.235.camel@rapid> <20071012184229.GL3379@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: "J. Mayer" , qemu-devel@nongnu.org Blue Swirl wrote: > On 10/12/07, Thiemo Seufer wrote: > > Blue Swirl wrote: > > [snip] > > > Index: qemu/linux-user/mipsn32/syscall.h > > > =================================================================== > > > --- qemu.orig/linux-user/mipsn32/syscall.h 2007-10-11 19:17:14.000000000 +0000 > > > +++ qemu/linux-user/mipsn32/syscall.h 2007-10-11 19:17:46.000000000 +0000 > > > @@ -4,15 +4,15 @@ > > > > > > struct target_pt_regs { > > > /* Saved main processor registers. */ > > > - target_ulong regs[32]; > > > + abi_ulong regs[32]; > > > > > > /* Saved special registers. */ > > > - target_ulong cp0_status; > > > - target_ulong lo; > > > - target_ulong hi; > > > - target_ulong cp0_badvaddr; > > > - target_ulong cp0_cause; > > > - target_ulong cp0_epc; > > > + abi_ulong cp0_status; > > > + abi_ulong lo; > > > + abi_ulong hi; > > > + abi_ulong cp0_badvaddr; > > > + abi_ulong cp0_cause; > > > + abi_ulong cp0_epc; > > > }; > > > > This is broken. n32 has 64bit wide registers (and uses them for long long). > > If target_ulong is 64 bits, then abi_ulong is 64 bits too and > therefore correct. Unless you want to enable the ABI32 feature? It is > only enabled for the new Sparc32plus and PPC targets for now. > > But I put the original target_ulongs back. I probably should have written "looks broken" than "is broken". In any case, having abi_ulong not matching the ABI's "unsigned long" is even more confusing than target_ulong not matching the ABI's "unsigned long". Now that I think of it again I believe the ABI32 feature isn't usable for mips. The ABI-mandated structures are too different. Thiemo