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Date: Sat, 13 Oct 2007 20:07:10 +0100
From: Thiemo Seufer <ths@networkno.de>
Subject: Re: [Fwd: Re: [Qemu-devel] RFC: Code fetch optimisation]
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To: "J. Mayer" <l_indien@magic.fr>
Cc: qemu-devel@nongnu.org

J. Mayer wrote:
[snip]
> > My idea of always using the ldx_code_p function is that we may have the
> > occasion to make it more cleaver and make the slow case handle code
> > execution in mmio areas, when it will be possible.
> 
> Here's an updated patch. I added a definition TARGET_HAS_VLE_INSNS which
> is defined is the cris, i386, m68k and ppcemb cases. Arm already has an
> explicit support for 32 bits thumb instructions spanning 2 pages, so it
> should not need this define. When this define is not set, the
> ldxxx_code_p function just does ldxxx_raw(phys_pc) in the softmmu case
> and ldxxx_raw(pc) in the user-mode only case. This is optimal for pure
> RISC architectures and does not need the #ifdef CONFIG_USER_ONLY you
> added for Sparc in your patch version. I also added a provision for a
> TARGET_MMIO_CODE define which may be used later when this will really be
> supported by Qemu.
> I also took your fixes for Sparc phys_pc computation, but reversed your
> patch to use ldl_raw as it should not be needed anymore.
> I did test PowerPC in user-mode only and softmmu mode and i386 in
> softmmu successfully using this new version of the patch.

Works ok for MIPS. There's no obvious change in performance, I guess
the slow TLB emulation drowns out any possible improvement.


Thiemo