From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IoPk3-0002Y2-Dm for qemu-devel@nongnu.org; Sat, 03 Nov 2007 16:37:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IoPk1-0002Tq-GU for qemu-devel@nongnu.org; Sat, 03 Nov 2007 16:37:14 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IoPk1-0002TZ-D7 for qemu-devel@nongnu.org; Sat, 03 Nov 2007 16:37:13 -0400 Received: from relay01.mx.bawue.net ([193.7.176.67]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IoPk0-0005DK-T6 for qemu-devel@nongnu.org; Sat, 03 Nov 2007 16:37:13 -0400 Date: Sat, 3 Nov 2007 20:37:07 +0000 From: Thiemo Seufer Subject: Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs Message-ID: <20071103203707.GG14756@networkno.de> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel Blue Swirl wrote: > Hi, > > RISC CPUs don't support self-modifying code unless the affected area > is flushed explicitly. Not entirely true. There are cacheless MIPS CPUs (the m4k), and also cache-snooping MIPS CPUs (the R1x000). > This patch disables the extra effort for SMC. > The changes in this version would affect all CPUs except x86, but I'd > like to see if there are problems with some target, so that the > committed change can be limited. Without comments, I'll just disable > SMC for Sparc, as there are no problems. So please comment, especially > if you want to "opt in". I prefer at least MIPS to stay as is. Thiemo