From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: Robert Reif <reif@earthlink.net>
Subject: Re: [Qemu-devel] sparc hflags support?
Date: Sun, 4 Nov 2007 23:47:46 +0000 [thread overview]
Message-ID: <200711042347.48438.paul@codesourcery.com> (raw)
In-Reply-To: <472E5919.80307@earthlink.net>
On Sunday 04 November 2007, Robert Reif wrote:
> I'm looking at adding more complete support for different sparc32
> CPUs, MMUs, cache controllers and systems.
>
> Each CPU/MMU/cache controller combination is slightly different and
> requires its own unique state. For example the two CPUs currently
> supported save the boot mode in different bits in the MMU control
> register: 0x2000 for the SuperSparc and 0x4000 for the TurboSparc.
> Others bits will need to be saved in the MMU and cache controllers
> as better hardware emulation is added.
If it's something that only changes rarely (e.g. when switching from early
boot to a real OS environment) you can just do a tb flush.
Does mmu/cache mode actually effect the instruction semantics?
Paul
next prev parent reply other threads:[~2007-11-04 23:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-11-04 23:43 [Qemu-devel] sparc hflags support? Robert Reif
2007-11-04 23:47 ` Paul Brook [this message]
2007-11-05 16:02 ` Blue Swirl
2007-11-05 15:55 ` Blue Swirl
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