From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Christoph Egger" <Christoph.Egger@amd.com>
Subject: [PATCH][SVM] handle MC threshold registers for Barcelona
Date: Thu, 22 Nov 2007 16:00:55 +0100
Message-ID: <200711221600.55649.Christoph.Egger@amd.com>
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Hi!

Subject says it all

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>


=2D-=20
AMD Saxony, Dresden, Germany
Operating System Research Center

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diff -r 980b8d1a5541 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c	Thu Nov 22 10:44:54 2007 +0000
+++ b/xen/arch/x86/hvm/svm/svm.c	Thu Nov 22 11:56:10 2007 +0100
@@ -133,6 +133,7 @@ static enum handler_return long_mode_do_
         break;
 
     case MSR_IA32_MC4_MISC: /* Threshold register */
+    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
         /*
          * MCA/MCE: Threshold register is reported to be locked, so we ignore
          * all write accesses. This behaviour matches real HW, so guests should
@@ -1777,6 +1778,7 @@ static void svm_do_msr_access(
             break;
 
         case MSR_IA32_MC4_MISC: /* Threshold register */
+        case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
             /*
              * MCA/MCE: We report that the threshold register is unavailable
              * for OS use (locked by the BIOS).

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