From: Tim Deegan <Tim.Deegan@citrix.com>
To: tgh <tianguanhua@ncic.ac.cn>
Cc: "Petersson, Mats" <Mats.Petersson@amd.com>,
xen-devel@lists.xensource.com,
Mark Williamson <mark.williamson@cl.cam.ac.uk>,
Daniel Stodden <stodden@cs.tum.edu>,
MT Rezaie <mmrezaie@gmail.com>
Subject: Re: page table question!
Date: Sun, 16 Dec 2007 11:55:10 +0000 [thread overview]
Message-ID: <20071216115510.GA25366@york.uk.xensource.com> (raw)
In-Reply-To: <47649685.2030709@ncic.ac.cn>
At 11:07 +0800 on 16 Dec (1197803269), tgh wrote:
> nested page table ,for the AMD NPT ,is stored in the dom0 linear space,
> not in the hypervisor virtual address ,is it? or what is the meaning of
> "that's one major benefit of nested paging: counteraction "address space
> compression".",and what about the Intel EPT, is it similar ,or how does
> it work, I am still comfused about the hypervisor' limited virtual
> address space, it wont be used for storing the EPT or NPT, is it? or
> what about the hypervisor's virtual address space in the AMD or
> Intel-vt?how much space is it? or what is tricks behind, could you give
> me a more detailed explanation about NPT and EPT
NPT is described in volume 2 of AMD's Architecture Programmer's Manual.
http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_739_7044,00.html
I don't know of any publically available documentation on EPT, but there
are some details in Jun Nakajima's slides from the recent Xen Summit.
http://xen.org/xensummit/xensummit_fall_2007.html
Tim.
--
Tim Deegan <Tim.Deegan@citrix.com>
Principal Software Engineer, Citrix Systems.
[Company #5334508: XenSource UK Ltd, reg'd c/o EC2Y 5EB, UK.]
next prev parent reply other threads:[~2007-12-16 11:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-13 14:55 page table question! MT Rezaie
2007-06-13 15:15 ` Petersson, Mats
2007-06-13 16:05 ` Mark Williamson
2007-06-13 16:22 ` Petersson, Mats
2007-06-13 16:35 ` Mark Williamson
2007-06-14 4:35 ` Jun Koi
2007-06-14 4:54 ` pradeep singh rautela
2007-06-14 8:27 ` Tim Deegan
2007-12-08 14:26 ` tgh
2007-12-08 14:36 ` Mark Williamson
2007-12-08 14:50 ` Daniel Stodden
2007-12-16 3:07 ` tgh
2007-12-16 11:55 ` Tim Deegan [this message]
2007-06-14 8:44 ` tgh
2007-06-14 9:51 ` Mark Williamson
2007-06-16 10:36 ` MT Rezaie
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