From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1J8giW-0005YR-0M for qemu-devel@nongnu.org; Sat, 29 Dec 2007 13:47:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1J8giT-0005Y5-DH for qemu-devel@nongnu.org; Sat, 29 Dec 2007 13:47:26 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1J8giT-0005Y2-7F for qemu-devel@nongnu.org; Sat, 29 Dec 2007 13:47:25 -0500 Received: from relay01.mx.bawue.net ([193.7.176.67]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1J8giS-0001CJ-Sm for qemu-devel@nongnu.org; Sat, 29 Dec 2007 13:47:25 -0500 Date: Sat, 29 Dec 2007 18:47:15 +0000 From: Thiemo Seufer Subject: Re: [Qemu-devel] MIPS COP1X (and related) instructions Message-ID: <20071229184714.GB18467@networkno.de> References: <87hci36mr3.fsf@firetop.home> <20071229013338.GA18467@networkno.de> <8763yh7tgx.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8763yh7tgx.fsf@firetop.home> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, rsandifo@nildram.co.uk Richard Sandiford wrote: > Thiemo Seufer writes: > > Richard Sandiford wrote: > >> All MIPS COP1X instructions currently require the FPU to be in 64-bit > >> mode. My understanding is that this is too restrictive, and that the > >> base conditions are different for different revisions of the ISA: > >> > >> MIPS IV: > >> COP1X instructions are available when the XX (CU3) bit of the > >> status register is set. This bit can be set independently of > >> UX and FR, and controls the core MIPS IV instructions as well > >> as the FPU ones. > > > > This part is, sadly, not fully correct. It depends on the CPU > > implementation what effect, the CU3 bit has. IIRC it behaves on some > > CPUs as you describe, while it is a nop on others. > > Sorry. I'll take your word for it. > > > (I don't know offhand which CPU did what there.) > > (FWIW, the r10k and VR5500 do as described, and I'm pretty sure the > RM7000 and RM9000 did too.) > > > Looks reasonable to me, apart from that one misassumption. > > What should the patch do instead for MIPS IV? Enable them unconditionally? Given that it is currently theoretical, as the only MIPS IV CPU supported is the VR5432: Add a comment to the MIPS IV test that it is too restrictive for some CPUs. Thiemo