From: Ralf Baechle <ralf@linux-mips.org>
To: Chris Friesen <cfriesen@nortel.com>
Cc: linux-mips@linux-mips.org
Subject: Re: quick question on 64-bit values with 32-bit inline assembly
Date: Tue, 22 Jan 2008 20:07:51 +0000 [thread overview]
Message-ID: <20080122200751.GA2672@linux-mips.org> (raw)
In-Reply-To: <47963C31.2000403@nortel.com>
On Tue, Jan 22, 2008 at 12:55:45PM -0600, Chris Friesen wrote:
>>> gethrtime(void)
>>> {
>>> unsigned long long result;
>>>
>>> asm volatile ("rdhwr %0,$31" : "=r" (result));
>
>> Ah, Cavium.
>
> Yes indeed. Any peculiarities that we should be watching out for? Previous
> mailing list threads would be great.
Cavium so far received little coverage on this list - but seems you're
about to start this. The reason why I was able to identify Cavium is that
afaics only Cavium is the only 64-bit CPU to implement a 64-bit timer in
hardware register $31.
The definition of rdhwr is generic and I think if anybody has considered
this specific interaction of ABI and processor architecture then it was
probably found not to implement such a special read because it is messy
in more than one way.
Ralf
next prev parent reply other threads:[~2008-01-22 20:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-21 18:09 quick question on 64-bit values with 32-bit inline assembly Chris Friesen
2008-01-22 17:57 ` Ralf Baechle
2008-01-22 18:02 ` Geert Uytterhoeven
2008-01-22 18:26 ` Ralf Baechle
2008-01-22 18:55 ` Chris Friesen
2008-01-22 20:07 ` Ralf Baechle [this message]
2008-01-28 21:02 ` M. Warner Losh
2008-01-28 21:18 ` Ralf Baechle
2008-01-28 21:26 ` M. Warner Losh
2008-01-29 10:16 ` Maciej W. Rozycki
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