From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andi Kleen <andi@firstfloor.org>
Subject: Re: [PATCH] [RFC] More fp instructions for realmode
	emulation (Enables booting OS/2 as a HVM guest on Intel/VT hardware)
Date: Mon, 3 Mar 2008 19:11:50 +0100
Message-ID: <20080303181149.GA13680@one.firstfloor.org>
References: <20080303165929.GC9853@one.firstfloor.org>
	<C3F1E625.1D616%keir.fraser@eu.citrix.com>
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To: Keir Fraser <keir.fraser@eu.citrix.com>
Cc: Andi Kleen <andi@firstfloor.org>, Trolle Selander <trolle.selander@gmail.com>, xen-devel <xen-devel@lists.xensource.com>
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> We don't trust FXRSTOR but we do trust FXSAVE. The AMD manual says that
> FXRSTOR will #GP if 1s are written to MXCSR reserved bits, but I take this
> to be a cut-and-paste typo since FXSAVE does not write to MXCSR.
> 
> If there's real evidence of FXSAVE causing #GP dependent on current FPU
> state, I'd be very happy to find out about it!

Sorry, double checked now the Intel docs. First I admit I don't 
quite remember why it was originally done in Linux, but they
both use exception handlers.

The Intel docs say that #MF can happen for a pending FPU exception
in 64bit mode.

-Andi