From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: [patch 05/24] QEMU/KVM: pci hotplug GPE support Date: Tue, 11 Mar 2008 17:11:56 -0300 Message-ID: <20080311201417.592220218@localhost.localdomain> References: <20080311201151.959635433@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Marcelo Tosatti To: qemu-devel@nongnu.org, kvm-devel@lists.sourceforge.net Return-path: Content-Disposition: inline; filename=acpi List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces@lists.sourceforge.net Errors-To: kvm-devel-bounces@lists.sourceforge.net List-Id: kvm.vger.kernel.org Enable the corresponding bit on the PCIST region and trigger the SCI. Signed-off-by: Marcelo Tosatti Index: kvm-userspace.hotplug2/qemu/hw/acpi.c =================================================================== --- kvm-userspace.hotplug2.orig/qemu/hw/acpi.c +++ kvm-userspace.hotplug2/qemu/hw/acpi.c @@ -538,6 +538,7 @@ void qemu_system_powerdown(void) #endif #define GPE_BASE 0xafe0 #define PROC_BASE 0xaf00 +#define PCI_BASE 0xae00 struct gpe_regs { uint16_t sts; /* status */ @@ -546,7 +547,13 @@ struct gpe_regs { uint8_t down; }; +struct pci_status { + uint32_t up; + uint32_t down; +}; + static struct gpe_regs gpe; +static struct pci_status pci0_status; static uint32_t gpe_readb(void *opaque, uint32_t addr) { @@ -614,6 +621,45 @@ static void gpe_writeb(void *opaque, uin #endif } +static uint32_t pcihotplug_read(void *opaque, uint32_t addr) +{ + uint32_t val = 0; + struct pci_status *g = opaque; + switch (addr) { + case PCI_BASE: + val = g->up; + break; + case PCI_BASE + 4: + val = g->down; + break; + default: + break; + } + +#if defined(DEBUG) + printf("pcihotplug read %lx == %lx\n", addr, val); +#endif + return val; +} + +static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) +{ + struct pci_status *g = opaque; + switch (addr) { + case PCI_BASE: + g->up = val; + break; + case PCI_BASE + 4: + g->down = val; + break; + } + +#if defined(DEBUG) + printf("pcihotplug write %lx <== %d\n", addr, val); +#endif +} + + static char *model; void qemu_system_hot_add_init(char *cpu_model) @@ -624,6 +670,9 @@ void qemu_system_hot_add_init(char *cpu_ register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe); register_ioport_read(PROC_BASE, 4, 1, gpe_readb, &gpe); + register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); + register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); + model = cpu_model; } @@ -665,3 +714,29 @@ void qemu_system_cpu_hot_add(int cpu, in disable_processor(&gpe, cpu); qemu_set_irq(pm_state->irq, 0); } + +static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) +{ + g->sts |= 2; + g->en |= 2; + p->up |= (1 << slot); +} + +static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) +{ + g->sts |= 2; + g->en |= 2; + p->down |= (1 << slot); +} + +void qemu_system_device_hot_add(int slot, int state) +{ + qemu_set_irq(pm_state->irq, 1); + pci0_status.up = 0; + pci0_status.down = 0; + if (state) + enable_device(&pci0_status, &gpe, slot); + else + disable_device(&pci0_status, &gpe, slot); + qemu_set_irq(pm_state->irq, 0); +} -- ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JZAtE-00079m-1c for qemu-devel@nongnu.org; Tue, 11 Mar 2008 16:16:00 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JZAtD-000799-Hw for qemu-devel@nongnu.org; Tue, 11 Mar 2008 16:15:59 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JZAtD-000790-6j for qemu-devel@nongnu.org; Tue, 11 Mar 2008 16:15:59 -0400 Received: from mx1.redhat.com ([66.187.233.31]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JZAtC-0003yw-TG for qemu-devel@nongnu.org; Tue, 11 Mar 2008 16:15:59 -0400 Message-Id: <20080311201417.592220218@localhost.localdomain> References: <20080311201151.959635433@localhost.localdomain> Date: Tue, 11 Mar 2008 17:11:56 -0300 From: Marcelo Tosatti Content-Disposition: inline; filename=acpi Subject: [Qemu-devel] [patch 05/24] QEMU/KVM: pci hotplug GPE support Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, kvm-devel@lists.sourceforge.net Cc: aliguori@us.ibm.com, Marcelo Tosatti Enable the corresponding bit on the PCIST region and trigger the SCI. Signed-off-by: Marcelo Tosatti Index: kvm-userspace.hotplug2/qemu/hw/acpi.c =================================================================== --- kvm-userspace.hotplug2.orig/qemu/hw/acpi.c +++ kvm-userspace.hotplug2/qemu/hw/acpi.c @@ -538,6 +538,7 @@ void qemu_system_powerdown(void) #endif #define GPE_BASE 0xafe0 #define PROC_BASE 0xaf00 +#define PCI_BASE 0xae00 struct gpe_regs { uint16_t sts; /* status */ @@ -546,7 +547,13 @@ struct gpe_regs { uint8_t down; }; +struct pci_status { + uint32_t up; + uint32_t down; +}; + static struct gpe_regs gpe; +static struct pci_status pci0_status; static uint32_t gpe_readb(void *opaque, uint32_t addr) { @@ -614,6 +621,45 @@ static void gpe_writeb(void *opaque, uin #endif } +static uint32_t pcihotplug_read(void *opaque, uint32_t addr) +{ + uint32_t val = 0; + struct pci_status *g = opaque; + switch (addr) { + case PCI_BASE: + val = g->up; + break; + case PCI_BASE + 4: + val = g->down; + break; + default: + break; + } + +#if defined(DEBUG) + printf("pcihotplug read %lx == %lx\n", addr, val); +#endif + return val; +} + +static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) +{ + struct pci_status *g = opaque; + switch (addr) { + case PCI_BASE: + g->up = val; + break; + case PCI_BASE + 4: + g->down = val; + break; + } + +#if defined(DEBUG) + printf("pcihotplug write %lx <== %d\n", addr, val); +#endif +} + + static char *model; void qemu_system_hot_add_init(char *cpu_model) @@ -624,6 +670,9 @@ void qemu_system_hot_add_init(char *cpu_ register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe); register_ioport_read(PROC_BASE, 4, 1, gpe_readb, &gpe); + register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); + register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); + model = cpu_model; } @@ -665,3 +714,29 @@ void qemu_system_cpu_hot_add(int cpu, in disable_processor(&gpe, cpu); qemu_set_irq(pm_state->irq, 0); } + +static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) +{ + g->sts |= 2; + g->en |= 2; + p->up |= (1 << slot); +} + +static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) +{ + g->sts |= 2; + g->en |= 2; + p->down |= (1 << slot); +} + +void qemu_system_device_hot_add(int slot, int state) +{ + qemu_set_irq(pm_state->irq, 1); + pci0_status.up = 0; + pci0_status.down = 0; + if (state) + enable_device(&pci0_status, &gpe, slot); + else + disable_device(&pci0_status, &gpe, slot); + qemu_set_irq(pm_state->irq, 0); +} --