Re: [PATCH] New DPLL clock framework.

[Tony Lindgren <tony@atomide.com>]

* Paul Walmsley <paul@booyaka.com> [080317 23:31]:
> On Thu, 13 Mar 2008, Roman Tereshonkov wrote:
> 
> > 	These changes is the result of the discussion with Paul Walmsley.
> > 	His ideas are included into this patch.
> > 
> > 	Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks,
> > 	and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk).
> > 	omap2_get_dpll_rate() now returns the correct DPLL rate, as represented
> > 	by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along
> > 	with high-frequency bypass support.
> > 
> > 	Add support for DPLLs function in locked and bypass clock modes.
> > 
> > Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
> 
> Looks good to me Roman, thanks.
> 
> Acked-by: Paul Walmsley <paul@pwsan.com>

Pushing today.

Tony