From: Ralf Baechle <ralf@linux-mips.org>
To: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Cc: linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH 1/2][MIPS] replace c0_compare acknowledge by c0_timer_ack()
Date: Tue, 18 Mar 2008 13:27:09 +0000 [thread overview]
Message-ID: <20080318132709.GC11382@linux-mips.org> (raw)
In-Reply-To: <200803180447.m2I4lJ40005091@po-mbox301.hop.2iij.net>
On Tue, Mar 18, 2008 at 01:47:20PM +0900, Yoichi Yuasa wrote:
> On Mon, 17 Mar 2008 16:16:35 +0000
> Ralf Baechle <ralf@linux-mips.org> wrote:
>
> > On Mon, Mar 17, 2008 at 11:47:40PM +0900, Yoichi Yuasa wrote:
> >
> > > VR41xx, CP0 hazard is necessary between read_c0_count() and write_c0_compare().
> >
> > Interesting. I wonder why you need this patch but nobody else?
>
> Three NOP are necessary on the TB0287(VR4131 board).
That much was obvious from your patch. I was more wondering about this
change:
- write_c0_compare(read_c0_count());
+ c0_timer_ack();
c0_timer_ack is defined as
static void c0_timer_ack(void)
{
write_c0_compare(read_c0_compare());
}
so your patch does a functional change there - even though it should not
actually matter. So I was wondering if for some reason you need that
change.
Just interested - it looks a bit cleaner so I'm leaning to apply this
change anyway.
Ralf
next prev parent reply other threads:[~2008-03-18 13:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-03-17 14:47 [PATCH 1/2][MIPS] replace c0_compare acknowledge by c0_timer_ack() Yoichi Yuasa
2008-03-17 14:49 ` [PATCH 2/2][MIPS] add irq_disable_hazard() before c0_compare_int_pending() Yoichi Yuasa
2008-03-17 16:16 ` [PATCH 1/2][MIPS] replace c0_compare acknowledge by c0_timer_ack() Ralf Baechle
2008-03-18 4:47 ` Yoichi Yuasa
2008-03-18 13:27 ` Ralf Baechle [this message]
2008-03-19 7:38 ` [PATCH][MIPS] add CP0 hazard to CP0 compare register accesses Yoichi Yuasa
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