Re: [PATCH] asoc tlv320aic33: skip usage of PLL in some cases

[Daniel Mack <daniel@caiaq.org>]

On Fri, Apr 18, 2008 at 04:47:16PM +0300, Jarkko Nikula wrote:
> > Ok, I agree. I changed that to find an appropriate value for Q
> > programmatically. Have a look at the attached patch, please. I hope i
> > finally got it now ;)
> 
> 
> That sounds a good idea. Then more cases will be covered.
> 
> What I noticed that instead of params_rate, I think we should compare here
> the FSref of 44.1 and 48 kHz (how about dual-rate mode?) when defining can
> the PLL be bypassed
> 
> if (params_rate(params) == aic3x->sysclk / (128 * pll_q))

Hmm? Why do you think so? I'm afraid I don't get your point here.

> Probably you forgot to move bypass case in this version after writing the
> AIC3X_SAMPLE_RATE_SEL_REG?

No, actually not.

> Spec is also saying that when NDAC is 1.5, 2.5, ... 5.5, then odd values of
> Q are not allowed.

NDAC and NADC are both hard-coded to 0 (divider of 1) at the moment.
Support for more flexible settings could be done in another step.
Also, the PLL setup could be done by calculation of values rather
that by a lookup table.

I'd like to see this patch applied now as base for further refinements.
Do you agree?

Daniel