From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JoQpu-000679-81 for qemu-devel@nongnu.org; Tue, 22 Apr 2008 18:19:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JoQpp-00066A-Hr for qemu-devel@nongnu.org; Tue, 22 Apr 2008 18:19:37 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JoQpp-000667-BD for qemu-devel@nongnu.org; Tue, 22 Apr 2008 18:19:33 -0400 Received: from mtaout02-winn.ispmail.ntl.com ([81.103.221.48]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JoQpp-0007Sf-1P for qemu-devel@nongnu.org; Tue, 22 Apr 2008 18:19:33 -0400 Received: from aamtaout03-winn.ispmail.ntl.com ([81.103.221.35]) by mtaout02-winn.ispmail.ntl.com with ESMTP id <20080422222248.YMYK17818.mtaout02-winn.ispmail.ntl.com@aamtaout03-winn.ispmail.ntl.com> for ; Tue, 22 Apr 2008 23:22:48 +0100 Received: from miranda.arrow ([213.107.26.151]) by aamtaout03-winn.ispmail.ntl.com with ESMTP id <20080422222628.ORSE26699.aamtaout03-winn.ispmail.ntl.com@miranda.arrow> for ; Tue, 22 Apr 2008 23:26:28 +0100 Received: from sdb by miranda.arrow with local (Exim 4.63) (envelope-from ) id 1JoQpg-00063I-R7 for qemu-devel@nongnu.org; Tue, 22 Apr 2008 23:19:24 +0100 Date: Tue, 22 Apr 2008 23:19:24 +0100 From: Stuart Brady Subject: Re: [Qemu-devel] [4239] x86/x86-64 MMU PAE fixes Message-ID: <20080422221924.GA23201@miranda.arrow> References: <200804222157.12963.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200804222157.12963.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tue, Apr 22, 2008 at 09:57:12PM +0100, Paul Brook wrote: > On Tuesday 22 April 2008, Aurelien Jarno wrote: > > -#define PHYS_ADDR_MASK 0xfffff000 > > +#define PHYS_ADDR_MASK (~0xfff) > > I think this is wrong. According to my docs physical addresses have an > architectural limit of 52 bits. Bits 52-62 of a PTE are reserved (must be > zero), and bit 63 is the NX bit. The documentation I'm using: "Intel 64 and IA-32 Architectures Software Development Manual, Volume 3A: System Programming Guide, Part 1" "3.8 36-Bit Physical Addressing Using The PAE Paging Mechanism" Lists bits 36-63 as "must be zero". (For i386, or x86_64 running in 32-bit mode.) "3.10 PAE-Enabled Paging in IA-32e Mode" Lists bits 40-51 as "must be zero". Lists bits 52 to 62 as "available". Lists bit 63 as "EXB" (i.e. the NX bit). (For x86_64 running in 64-bit mode.) HTH, -- Stuart Brady