From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>,
linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH][MIPS] fix divide by zero error in build_clear_page and build_copy_page
Date: Fri, 9 May 2008 09:49:26 +0100 [thread overview]
Message-ID: <20080509084926.GA14450@linux-mips.org> (raw)
In-Reply-To: <Pine.LNX.4.55.0805080003120.31409@cliff.in.clinika.pl>
On Thu, May 08, 2008 at 12:04:54AM +0100, Maciej W. Rozycki wrote:
> > > Why would ever cache_line_size be zero in this place? Are you trying to
> > > support a cacheless CPU? If not, it should be a BUG_ON().
> > >
> >
> > When CPU has no prefetch, no cache cdex_s and no caache cdex_p, cache_line_size is zero.
> > I confirmed it with Nevada(Cobalt server) and VR41xx.
>
> Fair enough. I confused the variable with some others used to store the
> actual line size of each of the caches. Your change is correct, thank you
> and sorry about the noise.
And I guess that means the variable should get a better name.
Ralf
next prev parent reply other threads:[~2008-05-09 8:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-07 14:38 [PATCH][MIPS] fix divide by zero error in build_clear_page and build_copy_page Yoichi Yuasa
2008-05-07 16:14 ` Maciej W. Rozycki
2008-05-07 22:38 ` Yoichi Yuasa
2008-05-07 23:04 ` Maciej W. Rozycki
2008-05-09 8:49 ` Ralf Baechle [this message]
2008-05-15 10:00 ` Ralf Baechle
2008-05-30 4:07 ` Atsushi Nemoto
2008-06-13 13:19 ` Ralf Baechle
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