From: Thiemo Seufer <ths@networkno.de>
To: qemu-devel@nongnu.org
Cc: paul@codesourcery.com, octane@alinto.com
Subject: Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)
Date: Thu, 22 May 2008 17:52:41 +0100 [thread overview]
Message-ID: <20080522165241.GA20195@networkno.de> (raw)
In-Reply-To: <20080522.101715.-233685094.imp@bsdimp.com>
M. Warner Losh wrote:
> In message: <200805221704.00480.paul@codesourcery.com>
> Paul Brook <paul@codesourcery.com> writes:
> : > : > I know that Cavium/octeon board are MIPS CPU.
> : > :
> : > : Not really. They're MIPS with extra weirdness.
> : >
> : > All SoCs are MIPS with extra documented weirdness. The OCTEON CPUs
> : > aren't documented in a public...
> :
> : The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA.
> : Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals.
>
> Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part.
AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr
with different instructions for unaligned load/stores. :-(
Thiemo
next prev parent reply other threads:[~2008-05-22 16:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-22 10:48 [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) octane indice
2008-05-22 13:27 ` Paul Brook
2008-05-22 15:55 ` M. Warner Losh
2008-05-22 16:03 ` Paul Brook
2008-05-22 16:17 ` M. Warner Losh
2008-05-22 16:52 ` Thiemo Seufer [this message]
2008-05-22 22:04 ` Jamie Lokier
2008-05-22 15:47 ` M. Warner Losh
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