From: Jamie Lokier <jamie@shareable.org>
To: qemu-devel@nongnu.org
Cc: paul@codesourcery.com, octane@alinto.com
Subject: Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)
Date: Thu, 22 May 2008 23:04:27 +0100 [thread overview]
Message-ID: <20080522220427.GA26229@shareable.org> (raw)
In-Reply-To: <20080522165241.GA20195@networkno.de>
Thiemo Seufer wrote:
> > Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part.
>
> AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr
> with different instructions for unaligned load/stores. :-(
The Alteon Tigon 2 gigabit ethernet processor did something similar,
except it wasn't a mode but fixed.
The documentation said it was because those particular instructions
are covered by a patent, so they couldn't implement them.
-- Jaie
next prev parent reply other threads:[~2008-05-22 22:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-22 10:48 [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) octane indice
2008-05-22 13:27 ` Paul Brook
2008-05-22 15:55 ` M. Warner Losh
2008-05-22 16:03 ` Paul Brook
2008-05-22 16:17 ` M. Warner Losh
2008-05-22 16:52 ` Thiemo Seufer
2008-05-22 22:04 ` Jamie Lokier [this message]
2008-05-22 15:47 ` M. Warner Losh
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