From: Pavel Machek <pavel@suse.cz>
To: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
LKML <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@elte.hu>,
Arjan van de Veen <arjan@infradead.org>,
"Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [patch 0/6] AMD C1E aware idle support
Date: Tue, 5 Aug 2008 19:42:18 +0200 [thread overview]
Message-ID: <20080805174217.GC8380@ucw.cz> (raw)
In-Reply-To: <20080704143536.GA21102@alberich.amd.com>
Hi!
> > > AMD CPUs with C1E support are currently excluded from high resolution
> > > timers and NOHZ support. The reason is that C1E is a BIOS controlled
> > > C3 power state which switches off TSC and the local APIC timer. The
> > > ACPI C-State control manages the TSC/local APIC timer wreckage, but
> > > this does not include the C1 based ("halt" instruction) C1E mode. The
> > > BIOS/SMM controlled C1E state works on most systems even without
> > > enabling ACPI C-State control.
> >
> > What a mess.
Yep, seems like AMD is breaking C1 semantics. Is it even valid from
ACPI spec point of view?
> > What is the measured power savings that justifies this effort?
>
> IMHO the power savings are not that important when such a kernel runs
> on bare metal:
Ok, so maybe we should disable C1E to work around its misdesign?
It would be certainly nice to have noc1e command line option...
> But overall no measurable difference in power usage was seen.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
next prev parent reply other threads:[~2008-08-05 17:42 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-06-12 10:28 [patch 0/6] AMD C1E aware idle support Thomas Gleixner
2008-06-12 10:28 ` [patch 1/6] x86: simplify idle selection Thomas Gleixner
2008-06-12 10:28 ` [patch 2/6] x86: cleanup C1E enabled detection Thomas Gleixner
2008-06-12 10:28 ` [patch 3/6] x86: use cpuinfo to check for interrupt pending message msr Thomas Gleixner
2008-06-13 6:55 ` Andreas Herrmann
2008-06-13 12:38 ` Thomas Gleixner
2008-06-13 14:28 ` Andreas Herrmann
2008-06-12 10:28 ` [patch 4/6] x86: use cpuid to check MWAIT support for C1 Thomas Gleixner
2008-06-12 10:28 ` [patch 5/6] x86: move more common idle functions/variables to process.c Thomas Gleixner
2008-06-12 10:29 ` [patch 6/6] x86: add c1e aware idle function Thomas Gleixner
2008-06-13 0:55 ` Andrew Morton
2008-06-13 6:02 ` Thomas Gleixner
2008-06-13 7:28 ` Andrew Morton
2008-06-18 19:21 ` Pavel Machek
2008-06-18 20:26 ` Rafael J. Wysocki
2008-06-18 21:58 ` Thomas Gleixner
2008-06-18 22:04 ` Rafael J. Wysocki
2008-06-18 22:17 ` Thomas Gleixner
2008-06-18 22:27 ` Rafael J. Wysocki
2008-06-12 12:31 ` [patch 0/6] AMD C1E aware idle support Rafael J. Wysocki
2008-06-12 12:32 ` Ingo Molnar
[not found] ` <200806131118.31160.rjw@sisk.pl>
2008-06-13 11:52 ` Rafael J. Wysocki
2008-06-12 13:09 ` Thomas Gleixner
2008-06-12 14:24 ` Andreas Herrmann
2008-06-12 15:48 ` Thomas Gleixner
2008-06-14 21:27 ` Maciej W. Rozycki
2008-06-18 22:47 ` Len Brown
2008-07-04 14:35 ` Andreas Herrmann
2008-07-04 15:18 ` [PATCH] x86: emphasize that c1e aware idle stuff is AMD specific Andreas Herrmann
2008-08-05 17:42 ` Pavel Machek [this message]
2008-08-06 13:21 ` [patch 0/6] AMD C1E aware idle support Andreas Herrmann
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