From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and Memory Queue settings for PPC 440SP/SPe and 460EX/GT/SX
Date: Tue, 12 Aug 2008 09:40:36 +0200 [thread overview]
Message-ID: <200808120940.36430.sr@denx.de> (raw)
In-Reply-To: <49c0ff980808111733w206b75adp5980146735435238@mail.gmail.com>
On Tuesday 12 August 2008, prodyut hazarika wrote:
> Read Pipeline depth should be set to 4 for PPC440SP/SPE, PPC405EX,
> PPC460EX/GT/SX processors.
> Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
> processors Please apply patch against next branch of Stefan's git tree.
>
> Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Patch is line-wrapped this time. I suggest that you use git-send-email to send
your git formatted patches.
Please find some more comments below.
> ---
> cpu/ppc4xx/44x_spd_ddr2.c | 28 +++++++++++++++++---
> cpu/ppc4xx/cpu_init.c | 21 ++++++++++++++-
> include/asm-ppc/ppc4xx-sdram.h | 48 +++++++++++++++++++++++-----------
> include/ppc440.h | 47 ----------------------------------
> include/ppc4xx.h | 55
> ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 131
> insertions(+), 68 deletions(-)
>
> diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
> index 1c36324..2ba7715 100644
> --- a/cpu/ppc4xx/44x_spd_ddr2.c
> +++ b/cpu/ppc4xx/44x_spd_ddr2.c
> @@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long
> *dimm_populated,
> unsigned long i;
> unsigned long bank_0_populated = 0;
> phys_size_t total_size = 0;
> +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
> + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
> + defined(CONFIG_460SX)
> + unsigned long val;
> +#endif
>
> /*------------------------------------------------------------------
> * Reset the rank_base_address.
> @@ -2249,18 +2254,33 @@ static void program_memory_queue(unsigned long
> *dimm_populated,
> }
> }
>
> -#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
> +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
> + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
> + defined(CONFIG_460SX)
> +
> /*
> - * Enable high bandwidth access on 460EX/GT.
> - * This should/could probably be done on other
> - * PPC's too, like 440SPe.
> + * Enable high bandwidth access
> * This is currently not used, but with this setup
> * it is possible to use it later on in e.g. the Linux
> * EMAC driver for performance gain.
> */
> mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
> mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
> +
> + /*
> + * Set optimal value for Memory Queue HB/LL Configuration registers
> + */
> +
> + val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
> SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
> + mtdcr(SDRAM_CONF1HB, val);
> +
> + val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
> SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
> + mtdcr(SDRAM_CONF1LL, val);
> +
> + val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
> + mtdcr(SDRAM_CONFPATHB, val);
> #endif
> +
Nitpick: Don't add this empty line here.
> }
>
>
> /*-------------------------------------------------------------------------
>----+ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
> index e2d0402..033d4f5 100644
> --- a/cpu/ppc4xx/cpu_init.c
> +++ b/cpu/ppc4xx/cpu_init.c
> @@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq)
> void
> cpu_init_f (void)
> {
> -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) ||
> defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) ||
> defined(CONFIG_440GX) ||
> defined(CONFIG_460EX) || \
> + defined(CONFIG_440SP) || defined(CONFIG_440SPE) ||
> defined(CONFIG_405EX) || \
> + defined (CONFIG_460GT) || defined(CONFIG_460SX)
No space after "defined" please. -> "defined("
> u32 val;
> #endif
>
> @@ -301,6 +303,23 @@ cpu_init_f (void)
> val |= 0x400;
> mtsdr(SDR0_USB2HOST_CFG, val);
> #endif /* CONFIG_460EX */
> +
> +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
> + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
> + defined(CONFIG_405EX) || defined(CONFIG_460SX)
Why don't you add 440GP and 440GX here? From my understanding they would
benefit from this pipeline change too.
> +
> + /*
> + * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
> + */
> +
> + val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
> + mtdcr(plb0_acr, val);
> +
> + val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
> + mtdcr(plb1_acr, val);
> +
> +#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
> +
Again, please don't add this empty line here before the "}".
> }
>
> /*
> diff --git a/include/asm-ppc/ppc4xx-sdram.h
> b/include/asm-ppc/ppc4xx-sdram.h index df787b3..d2e3b42 100644
> --- a/include/asm-ppc/ppc4xx-sdram.h
> +++ b/include/asm-ppc/ppc4xx-sdram.h
> @@ -259,23 +259,39 @@
> /*
> * Memory queue defines
> */
> -#define SDRAMQ_DCR_BASE 0x040
> -
> -#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size
> */ -#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size
> */ -#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address &
> size */ -#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address
> & size */ -#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1
> HB */ -#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error
> status HB */ -#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /*
> error address upper 32 HB */ -#define
> SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
> -#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32
> LL */
> -#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL
> */ -#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL
> */ -#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address
> upper 32 LL */ -#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error
> address lower 32 LL */ -#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /*
> configuration between paths */ -#define
> SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
> +#define SDRAMQ_DCR_BASE 0x040
> +
> +#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base
> address & size */
> +#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base
> address & size */
> +#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base
> address & size */
> +#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base
> address & size */
> +#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB
> */
> +#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on
> First Request - Bit 0 */
> +#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline
> Disable - Bit 12 */
> +#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline
> Disable - Bit 13 */
> +#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14
> */ +#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing
> Enable - Bit 20 */
> +#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through
> Enable - Bit 21 */
> +
> +#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB
> */
> +#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address
> upper 32 HB */
> +#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address
> lower 32 HB */
> +#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address
> upper 32 LL */
> +#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL
> */
> +#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on
> First Request - Bit 0 */
> +#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline
> Disable - Bit 12 */
> +#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline
> Disable - Bit 13 */
> +#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14
> */ +#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing
> Enable - Bit 20 */
> +#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through
> Enable - Bit 21 */
> +
> +#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL
> */
> +#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address
> upper 32 LL */
> +#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address
> lower 32 LL */
> +#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration
> between paths */
> +#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction
> Passing Enable - Bit 4 */
> +
> +#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address
> upper 32 LL */
>
> #if !defined(CONFIG_405EX)
> /*
> diff --git a/include/ppc440.h b/include/ppc440.h
> index 92db15f..3584fd2 100644
> --- a/include/ppc440.h
> +++ b/include/ppc440.h
> @@ -341,53 +341,6 @@
>
> #define PLB4_ACR_WRP (0x80000000 >> 7)
>
> -/* Nebula PLB4 Arbiter - PowerPC440EP */
> -#define PLB_ARBITER_BASE 0x80
> -
> -#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
> -#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
> -#define plb0_acr_ppm_mask 0xF0000000
> -#define plb0_acr_ppm_fixed 0x00000000
> -#define plb0_acr_ppm_fair 0xD0000000
> -#define plb0_acr_hbu_mask 0x08000000
> -#define plb0_acr_hbu_disabled 0x00000000
> -#define plb0_acr_hbu_enabled 0x08000000
> -#define plb0_acr_rdp_mask 0x06000000
> -#define plb0_acr_rdp_disabled 0x00000000
> -#define plb0_acr_rdp_2deep 0x02000000
> -#define plb0_acr_rdp_3deep 0x04000000
> -#define plb0_acr_rdp_4deep 0x06000000
> -#define plb0_acr_wrp_mask 0x01000000
> -#define plb0_acr_wrp_disabled 0x00000000
> -#define plb0_acr_wrp_2deep 0x01000000
> -
> -#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
> -#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
> -#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
> -#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
> -#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
> -
> -#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
> -#define plb1_acr_ppm_mask 0xF0000000
> -#define plb1_acr_ppm_fixed 0x00000000
> -#define plb1_acr_ppm_fair 0xD0000000
> -#define plb1_acr_hbu_mask 0x08000000
> -#define plb1_acr_hbu_disabled 0x00000000
> -#define plb1_acr_hbu_enabled 0x08000000
> -#define plb1_acr_rdp_mask 0x06000000
> -#define plb1_acr_rdp_disabled 0x00000000
> -#define plb1_acr_rdp_2deep 0x02000000
> -#define plb1_acr_rdp_3deep 0x04000000
> -#define plb1_acr_rdp_4deep 0x06000000
> -#define plb1_acr_wrp_mask 0x01000000
> -#define plb1_acr_wrp_disabled 0x00000000
> -#define plb1_acr_wrp_2deep 0x01000000
> -
> -#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
> -#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
> -#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
> -#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
> -
> /* Pin Function Control Register 1 */
> #define SDR0_PFC1 0x4101
> #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable
> */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h
> index c71da60..154956e 100644
> --- a/include/ppc4xx.h
> +++ b/include/ppc4xx.h
> @@ -46,6 +46,61 @@
> #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
> #endif
>
> +/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
> +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
> + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
> + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
> + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
> + defined(CONFIG_460SX) || defined(CONFIG_405EX)
> +
> +#define PLB_ARBITER_BASE 0x80
> +
> +#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
> +#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
No upper case defines in this patch. I'm fine with this as long as we update
this in a later patch.
And from a quick check of the manuals the 440GP/GX have a slightly different
register layout. Is this the reason you didn't include those PPC's in this
patch version? What are your plans for those PPC's?
Thanks.
Best regards,
Stefan
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next prev parent reply other threads:[~2008-08-12 7:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-08-12 0:33 [U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and Memory Queue settings for PPC 440SP/SPe and 460EX/GT/SX prodyut hazarika
2008-08-12 7:40 ` Stefan Roese [this message]
2008-08-12 13:36 ` Prodyut Hazarika
2008-08-12 13:45 ` Stefan Roese
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