Re: RFC [PATCH] x86/pci: reserve extra page to avoid error caused by P2P pref DMA reads

[Ingo Molnar <mingo@elte.hu>]

* Yinghai Lu <yhlu.kernel@gmail.com> wrote:

> Diag guys, found one system when loading is high, will have gart wark 
> error. root cause is P2P bridge try to prefetch for several intel 
> e1000 under it. and that skb is near GART iommu area.
> 
> try to reserve page in the boundary at first. last page near TOM2, and 
> last page near MMIO also gart first and last page.
> 
> need one better way for all arch support PCI and memory with a lot of 
> holes etc.

>  void __init dma32_reserve_bootmem(void)
>  {
>  	unsigned long size, align;
> +
> +	/*
> +	 * try to reserve last page to workaround P2P bridge pref DMA reads
> +	 * normally don't need to reserve the page near mmio,
> +	 * because always has acpi etc sit there.
> +	 * but some system has that acpi in the middle of ram below 4g
> +	 * so just reserve it.
> +	 */

Nice! Could this be the root cause of those skb corruptions and e1000 
crashes you've been reporting? So the _usual_ setup accidentally 
protects us from these prefetch induced failures.

I think your patch is fine for the iommu bits, but the 
reserve_last_page() thing should be done in a cleaner way. Cannot we 
just reserve it all at the e820 stage, before passing that RAM to the 
bootmem allocator?

Also, what is the guarantee that 4K of a space is enough to stop all 
prefetching across that boundary?

	Ingo