Re: [Qemu-devel] TCG: 64-bit temporaries on 32-bit target?

[Thiemo Seufer <ths@networkno.de>]

Andreas Färber wrote:
> Hello,
>
> On PowerPC there appear to be some "SPE" instructions that operate on  
> 64-bit registers while the rest of the target is 32-bit. In dyngen code, 
> they can easily use T0_64 then.
>
> In TCG however, cpu_T[0] is tl==i32 for ppc, only for ppc64 would  
> cpu_T[0] work due to tl==i64. At the same time I was told I can't use  
> tcg_gen_movi_i32 for tl cpu_T[n], so it seems we can't just  
> unconditionally use i64 for cpu_T[0..2] either?
>
> This issue prevents dyngen op_load_gpr_{T0,T1} from being removed  
> because ppc64 gen_op_load_gpr64_{T0,T1} reuses them.
>
> Any suggestions appreciated!

A similiar problem exists for MIPS32 with 64-bit FPU, I introduced
e.g T64_0 and T64_1 and added explicit conversions to 32-bit registers/
register pairs where necessary.


Thiemo