From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KbFzs-0007VT-MX for qemu-devel@nongnu.org; Thu, 04 Sep 2008 10:39:44 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KbFzq-0007Uh-2l for qemu-devel@nongnu.org; Thu, 04 Sep 2008 10:39:44 -0400 Received: from [199.232.76.173] (port=50423 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KbFzp-0007UZ-DN for qemu-devel@nongnu.org; Thu, 04 Sep 2008 10:39:41 -0400 Received: from hall.aurel32.net ([91.121.138.14]:60859) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KbFzp-0006aN-03 for qemu-devel@nongnu.org; Thu, 04 Sep 2008 10:39:41 -0400 Received: from junta-icatm144570-bada.red.retevision.es ([62.81.118.18] helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1KbFzl-00032t-LM for qemu-devel@nongnu.org; Thu, 04 Sep 2008 16:39:38 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1KbFzf-0003p8-Nv for qemu-devel@nongnu.org; Thu, 04 Sep 2008 16:39:31 +0200 Date: Thu, 4 Sep 2008 16:39:31 +0200 From: =?iso-8859-15?Q?Aur=E9lien?= Jarno Subject: Re: [Qemu-devel] [PATCH 7/x] ppc: Convert FPR moves to TCG Message-ID: <20080904143931.GC11924@volta.aurel32.net> References: <20080903050757.GX4681@volta.aurel32.net> <20080903112840.GC17474@networkno.de> <7F235F5C-A1C9-4617-8C8D-900778862BBD@web.de> <67BC3D0E-6819-426A-BD93-ADE75621E6E4@web.de> <3D7FC18B-1027-4AB9-ACDE-E7B650F259F2@googlemail.com> <519F0BAB-FCDE-40D4-9255-48CB569909E5@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <519F0BAB-FCDE-40D4-9255-48CB569909E5@googlemail.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Thu, Sep 04, 2008 at 04:08:05PM +0200, Andreas Färber wrote: > Replace op_{load,store}_fpr with tcg_gen_mov_i64. > Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2]. > > This obsoletes op_template.h for REG > 7. Applied, thanks. > > Signed-off-by: Andreas Faerber > > --- > target-ppc/op.c | 72 -------------------------- > target-ppc/op_template.h | 50 ------------------ > target-ppc/translate.c | 125 +++++++++++++++++++++++ > +---------------------- > 3 files changed, 65 insertions(+), 182 deletions(-) > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index e663e60..107817c 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -50,78 +50,6 @@ > #define REG 7 > #include "op_template.h" > > -#define REG 8 > -#include "op_template.h" > - > -#define REG 9 > -#include "op_template.h" > - > -#define REG 10 > -#include "op_template.h" > - > -#define REG 11 > -#include "op_template.h" > - > -#define REG 12 > -#include "op_template.h" > - > -#define REG 13 > -#include "op_template.h" > - > -#define REG 14 > -#include "op_template.h" > - > -#define REG 15 > -#include "op_template.h" > - > -#define REG 16 > -#include "op_template.h" > - > -#define REG 17 > -#include "op_template.h" > - > -#define REG 18 > -#include "op_template.h" > - > -#define REG 19 > -#include "op_template.h" > - > -#define REG 20 > -#include "op_template.h" > - > -#define REG 21 > -#include "op_template.h" > - > -#define REG 22 > -#include "op_template.h" > - > -#define REG 23 > -#include "op_template.h" > - > -#define REG 24 > -#include "op_template.h" > - > -#define REG 25 > -#include "op_template.h" > - > -#define REG 26 > -#include "op_template.h" > - > -#define REG 27 > -#include "op_template.h" > - > -#define REG 28 > -#include "op_template.h" > - > -#define REG 29 > -#include "op_template.h" > - > -#define REG 30 > -#include "op_template.h" > - > -#define REG 31 > -#include "op_template.h" > - > void OPPROTO op_print_mem_EA (void) > { > do_print_mem_EA(T0); > diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h > index 64e38a9..0501256 100644 > --- a/target-ppc/op_template.h > +++ b/target-ppc/op_template.h > @@ -18,7 +18,6 @@ > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 > USA > */ > > -#if REG <= 7 > /* Condition register moves */ > void OPPROTO glue(op_load_crf_T0_crf, REG) (void) > { > @@ -38,53 +37,4 @@ void OPPROTO glue(op_store_T0_crf_crf, REG) (void) > RETURN(); > } > > -#if 0 // Unused > -void OPPROTO glue(op_store_T1_crf_crf, REG) (void) > -{ > - env->crf[REG] = T1; > - RETURN(); > -} > -#endif > - > -#endif /* REG <= 7 */ > - > -/* floating point registers moves */ > -void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void) > -{ > - FT0 = env->fpr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void) > -{ > - env->fpr[REG] = FT0; > - RETURN(); > -} > - > -void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void) > -{ > - FT1 = env->fpr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void) > -{ > - env->fpr[REG] = FT1; > - RETURN(); > -} > - > -void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void) > -{ > - FT2 = env->fpr[REG]; > - RETURN(); > -} > - > -#if 0 // unused > -void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void) > -{ > - env->fpr[REG] = FT2; > - RETURN(); > -} > -#endif > - > #undef REG > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 0674376..dcb64b4 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -50,11 +50,13 @@ static char cpu_reg_names[10*3 + 22*4 /* GPR */ > #if !defined(TARGET_PPC64) > + 10*4 + 22*5 /* SPE GPRh */ > #endif > + + 10*4 + 22*5 /* FPR */ > + 2*(10*6 + 22*7) /* AVRh, AVRl */]; > static TCGv cpu_gpr[32]; > #if !defined(TARGET_PPC64) > static TCGv cpu_gprh[32]; > #endif > +static TCGv cpu_fpr[32]; > static TCGv cpu_avrh[32], cpu_avrl[32]; > > /* dyngen register indexes */ > @@ -64,6 +66,7 @@ static TCGv cpu_T[3]; > #else > static TCGv cpu_T64[3]; > #endif > +static TCGv cpu_FT[3]; > static TCGv cpu_AVRh[3], cpu_AVRl[3]; > > #include "gen-icount.h" > @@ -101,6 +104,14 @@ void ppc_translate_init(void) > TCG_AREG0, offsetof(CPUState, > t2_64), > "T2_64"); > #endif > + > + cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, ft0), "FT0"); > + cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, ft1), "FT1"); > + cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, ft2), "FT2"); > + > cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > offsetof(CPUState, avr0.u64[0]), > "AVR0H"); > cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > @@ -127,6 +138,10 @@ void ppc_translate_init(void) > p += (i < 10) ? 4 : 5; > #endif > > + sprintf(p, "fp%d", i); > + cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, fpr[i]), p); > + > sprintf(p, "avr%dH", i); > cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > offsetof(CPUState, > avr[i].u64[0]), p); > @@ -196,16 +211,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); > GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); > #endif > > -/* floating point registers moves */ > -GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); > -GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); > -GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); > -GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); > -GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); > -#if 0 // unused > -GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); > -#endif > - > /* internal defines */ > typedef struct DisasContext { > struct TranslationBlock *tb; > @@ -1780,15 +1785,15 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > \ > - gen_op_load_fpr_FT1(rC(ctx->opcode)); > \ > - gen_op_load_fpr_FT2(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##op(); > \ > if (isfloat) { > \ > gen_op_frsp(); > \ > } \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > > @@ -1803,14 +1808,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > \ > - gen_op_load_fpr_FT1(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##op(); > \ > if (isfloat) { > \ > gen_op_frsp(); > \ > } \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) > \ > @@ -1824,14 +1829,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > \ > - gen_op_load_fpr_FT1(rC(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##op(); > \ > if (isfloat) { > \ > gen_op_frsp(); > \ > } \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) > \ > @@ -1845,10 +1850,10 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##name(); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > > @@ -1859,10 +1864,10 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##name(); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > > @@ -1902,10 +1907,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, > PPC_FLOAT_FSQRT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fsqrt(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(1, Rc(ctx->opcode) != 0); > } > > @@ -1915,11 +1920,11 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, > 0x001F07C0, PPC_FLOAT_FSQRT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fsqrt(); > gen_op_frsp(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(1, Rc(ctx->opcode) != 0); > } > > @@ -1966,8 +1971,8 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, > PPC_FLOAT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > - gen_op_load_fpr_FT1(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fcmpo(); > gen_op_store_T0_crf(crfD(ctx->opcode)); > @@ -1981,8 +1986,8 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, > PPC_FLOAT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > - gen_op_load_fpr_FT1(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fcmpu(); > gen_op_store_T0_crf(crfD(ctx->opcode)); > @@ -2002,8 +2007,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, > PPC_FLOAT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(0, Rc(ctx->opcode) != 0); > } > > @@ -2041,7 +2046,7 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, > PPC_FLOAT) > gen_optimize_fprf(); > gen_reset_fpstatus(); > gen_op_load_fpscr_FT0(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(0, Rc(ctx->opcode) != 0); > } > > @@ -2096,7 +2101,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, > PPC_FLOAT) > return; > } > gen_optimize_fprf(); > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_store_fpscr(FM(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) { > @@ -2716,7 +2721,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, > type) \ > } \ > gen_addr_imm_index(ctx, 0); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > } > > #define GEN_LDUF(width, opc, type) > \ > @@ -2732,7 +2737,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, > 0x00000000, type) \ > } \ > gen_addr_imm_index(ctx, 0); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > > @@ -2749,7 +2754,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, > 0x00000001, type) \ > } \ > gen_addr_reg_index(ctx); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > > @@ -2762,7 +2767,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, > 0x00000001, type) \ > } \ > gen_addr_reg_index(ctx); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > } > > #define GEN_LDFS(width, op, type) > \ > @@ -2786,7 +2791,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, > 0x00000000, type) \ > return; > \ > } \ > gen_addr_imm_index(ctx, 0); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > } > > @@ -2802,7 +2807,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, > 0x00000000, type) \ > return; > \ > } \ > gen_addr_imm_index(ctx, 0); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > @@ -2819,7 +2824,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, > 0x00000001, type) \ > return; > \ > } \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > @@ -2832,7 +2837,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, > 0x00000001, type) \ > return; > \ > } \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > } > > @@ -4522,8 +4527,8 @@ GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > } > > /* lfqu */ > @@ -4535,8 +4540,8 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > } > @@ -4550,8 +4555,8 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > } > @@ -4563,8 +4568,8 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > } > > /* stfq */ > @@ -4573,8 +4578,8 @@ GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > } > > @@ -4586,8 +4591,8 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > @@ -4601,8 +4606,8 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > @@ -4614,8 +4619,8 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > } > > -- > 1.5.5.1 > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net