From: venkatesh.pallipadi@intel.com
To: mingo@elte.hu, tglx@linutronix.de, hpa@zytor.com
Cc: linux-kernel@vger.kernel.org, shaohua.li@intel.com
Subject: [RFC 0/4] Using HPET in MSI mode and setting up per CPU HPET timers
Date: Fri, 05 Sep 2008 18:02:14 -0700 [thread overview]
Message-ID: <20080906010214.229910000@intel.com> (raw)
Patchset that uses HPET timers in MSI mode (when supported) and sets up per
CPU HPET timers. This removes the dependency on IRQ0 timer broadcast with LAPIC
stopping in deep C-state, on platforms that support HPET MSI mode.
On my test system with dual core CPU, the number of timer related interrupts
(HPET_MSI + IRQ0 + LAPIC) comes down from 180 to 95 over a period of 10s,
with these patches.
This is on an idle system with tickless enabled and when system is idle.
Patches against tip.
--
next reply other threads:[~2008-09-06 1:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-06 1:02 venkatesh.pallipadi [this message]
2008-09-06 1:02 ` [RFC 1/4] x86: HPET_MSI change IRQ affinity in process context when it is disabled venkatesh.pallipadi
2008-09-06 1:02 ` [RFC 2/4] x86: HPET_MSI Refactor code in preparation for HPET_MSI venkatesh.pallipadi
2008-09-06 1:02 ` [RFC 3/4] x86: HPET_MSI Basic HPET_MSI setup code venkatesh.pallipadi
2008-09-06 1:02 ` [RFC 4/4] x86: HPET_MSI Initialise per-cpu HPET timers venkatesh.pallipadi
2008-09-06 12:42 ` [RFC 0/4] Using HPET in MSI mode and setting up per CPU " Ingo Molnar
2008-09-06 13:03 ` Ingo Molnar
2008-09-08 17:18 ` Venki Pallipadi
2008-09-08 17:55 ` Ingo Molnar
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