Re: [PATCH] x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC

[Andreas Herrmann <andreas.herrmann3@amd.com>]

On Thu, Sep 18, 2008 at 03:35:32PM -0400, Valdis.Kletnieks@vt.edu wrote:
> On Thu, 18 Sep 2008 21:12:10 +0200, Andreas Herrmann said:
> > .. otherwise TSC is marked unstable on AMD family 0x10 and 0x11 CPUs.
> 
> OK.  I'll bite (admittedly not having looked at the actual code yet).
> 
> If the TSC is in fact invariant, what's causing the kernel to mark it as
> unstable?

Guess, you should have a look at the code.

TSC on K8 is not P-state and C-state invariant.
Thus on K8 you'll have a TSC drift if C1E is entered.

This means that if C1E is enabled TSC should be marked unstable on
those CPUs (it shouldn't be used as a clocksource).

> Sounds almost like a bug being papered over here...

Not sure what you mean.

Currently the kernel assumes TSC is stable and there are various
places where Linux might spot when TSC is unstable. c1e_idle is one
such place. But it's wrong to mark TSC unstable for all AMD CPUs in
this function as newer CPU families have TSC's that are P- and C-state
invariant.


Regards,

Andreas