Re: [PATCH] OMAP3 clock: put DPLL into bypass if bypass rate = clk->rate, not hardware rate

[Tony Lindgren <tony@atomide.com>]

* Paul Walmsley <paul@pwsan.com> [080925 17:40]:
> 
> When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use
> the user's desired rate in clk->rate to determine whether to put the
> DPLL into bypass or lock mode, rather than reading the DPLL's current
> idle state from its hardware registers.
> 
> This fixes a bug observed when leaving retention. Non-CORE DPLLs were
> not being relocked when downstream clocks re-enabled; rather, the DPLL
> entered bypass mode.
> 
> Problem reported by Tero Kristo <tero.kristo@nokia.com>.

Pushing.

Tony

> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/mach-omap2/clock34xx.c |    4 +---
>  1 files changed, 1 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index c89d6bc..df258f7 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -281,9 +281,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk)
>  	if (!dd)
>  		return -EINVAL;
>  
> -	rate = omap2_get_dpll_rate(clk);
> -
> -	if (dd->bypass_clk->rate == rate)
> +	if (clk->rate == dd->bypass_clk->rate)
>  		r = _omap3_noncore_dpll_bypass(clk);
>  	else
>  		r = _omap3_noncore_dpll_lock(clk);
> --
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