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diff for duplicates of <20081007000225.GA26529@linux-os.sc.intel.com>

diff --git a/a/1.txt b/N1/1.txt
index bf988c1..5de4120 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -503,7 +503,7 @@ index 5d1eb7e..8cc2f8a 100644
 +	for (i = 0; i < nentries; i++) {
 +		hdr = __va(xsdt->table_offset_entry[i]);
 +		if (strncmp(hdr->signature, ACPI_SIG_DMAR,
-+			sizeof(ACPI_SIG_DMAR) - 1) = 0)
++			sizeof(ACPI_SIG_DMAR) - 1) == 0)
 +			return "dig_vtd";
 +	}
 +#endif
@@ -586,12 +586,14 @@ index 60c6ef6..702a09c 100644
 +	dest = cpu_physical_id(first_cpu(mask));
 +
 +	msg->address_hi = 0;
-+	msg->address_lo +		MSI_ADDR_HEADER |
++	msg->address_lo =
++		MSI_ADDR_HEADER |
 +		MSI_ADDR_DESTMODE_PHYS |
 +		MSI_ADDR_REDIRECTION_CPU |
 +		MSI_ADDR_DESTID_CPU(dest);
 +
-+	msg->data +		MSI_DATA_TRIGGER_EDGE |
++	msg->data =
++		MSI_DATA_TRIGGER_EDGE |
 +		MSI_DATA_LEVEL_ASSERT |
 +		MSI_DATA_DELIVERY_FIXED |
 +		MSI_DATA_VECTOR(cfg->vector);
@@ -928,7 +930,8 @@ index 2a0d27f..2c1a948 100644
 +	shl	r21=r21,r20		// r21: stride size of the i-cache(s)
 +	;;
 +	sub	r8=r22,r23		// number of strides - 1
-+	shl	r24=r23,r20		// r24: addresses for "fc" +					//	"start" rounded down to stride
++	shl	r24=r23,r20		// r24: addresses for "fc" =
++					//	"start" rounded down to stride
 +					//	boundary
 +	.save	ar.lc,r3
 +	mov	r3=ar.lc		// save ar.lc
diff --git a/a/content_digest b/N1/content_digest
index 8a244e1..3feda00 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,7 +1,7 @@
  "ref\020081001165750.GA21272@linux-os.sc.intel.com\0"
  "From\0Fenghua Yu <fenghua.yu@intel.com>\0"
  "Subject\0[PATCH V2 2/2] Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part\0"
- "Date\0Tue, 07 Oct 2008 00:02:25 +0000\0"
+ "Date\0Mon, 6 Oct 2008 17:02:25 -0700\0"
  "To\0Luck"
   Tony <tony.luck@intel.com>
   Jesse Barnes <jbarnes@virtuousgeek.org>
@@ -520,7 +520,7 @@
  "+\tfor (i = 0; i < nentries; i++) {\n"
  "+\t\thdr = __va(xsdt->table_offset_entry[i]);\n"
  "+\t\tif (strncmp(hdr->signature, ACPI_SIG_DMAR,\n"
- "+\t\t\tsizeof(ACPI_SIG_DMAR) - 1) = 0)\n"
+ "+\t\t\tsizeof(ACPI_SIG_DMAR) - 1) == 0)\n"
  "+\t\t\treturn \"dig_vtd\";\n"
  "+\t}\n"
  "+#endif\n"
@@ -603,12 +603,14 @@
  "+\tdest = cpu_physical_id(first_cpu(mask));\n"
  "+\n"
  "+\tmsg->address_hi = 0;\n"
- "+\tmsg->address_lo +\t\tMSI_ADDR_HEADER |\n"
+ "+\tmsg->address_lo =\n"
+ "+\t\tMSI_ADDR_HEADER |\n"
  "+\t\tMSI_ADDR_DESTMODE_PHYS |\n"
  "+\t\tMSI_ADDR_REDIRECTION_CPU |\n"
  "+\t\tMSI_ADDR_DESTID_CPU(dest);\n"
  "+\n"
- "+\tmsg->data +\t\tMSI_DATA_TRIGGER_EDGE |\n"
+ "+\tmsg->data =\n"
+ "+\t\tMSI_DATA_TRIGGER_EDGE |\n"
  "+\t\tMSI_DATA_LEVEL_ASSERT |\n"
  "+\t\tMSI_DATA_DELIVERY_FIXED |\n"
  "+\t\tMSI_DATA_VECTOR(cfg->vector);\n"
@@ -945,7 +947,8 @@
  "+\tshl\tr21=r21,r20\t\t// r21: stride size of the i-cache(s)\n"
  "+\t;;\n"
  "+\tsub\tr8=r22,r23\t\t// number of strides - 1\n"
- "+\tshl\tr24=r23,r20\t\t// r24: addresses for \"fc\" +\t\t\t\t\t//\t\"start\" rounded down to stride\n"
+ "+\tshl\tr24=r23,r20\t\t// r24: addresses for \"fc\" =\n"
+ "+\t\t\t\t\t//\t\"start\" rounded down to stride\n"
  "+\t\t\t\t\t//\tboundary\n"
  "+\t.save\tar.lc,r3\n"
  "+\tmov\tr3=ar.lc\t\t// save ar.lc\n"
@@ -971,4 +974,4 @@
  "+\tbr.ret.sptk.many rp\n"
  +END(clflush_cache_range)
 
-8e4c45005cd60908d8cbb51821b6fd76857e1ca59dff1572894df0f18d7ab893
+37847a76df49a522a32c4859e0d6fc1e9a5552402a6ab2278bbb43d6748d0cce

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