From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KoiuU-0005Mw-JC for qemu-devel@nongnu.org; Sat, 11 Oct 2008 14:09:50 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KoiuT-0005Mj-FF for qemu-devel@nongnu.org; Sat, 11 Oct 2008 14:09:49 -0400 Received: from [199.232.76.173] (port=47198 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KoiuT-0005Mg-C5 for qemu-devel@nongnu.org; Sat, 11 Oct 2008 14:09:49 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:33483) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KoiuT-00013Q-0G for qemu-devel@nongnu.org; Sat, 11 Oct 2008 14:09:49 -0400 From: Paul Brook Date: Sat, 11 Oct 2008 19:09:35 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200810111909.36022.paul@codesourcery.com> Subject: [Qemu-devel] GDB stub changes Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org I've just committed changes to the qemu gdb remote protocol implementation that add support for XML register descriptions. This is a relatively new GDB feature that allows qemu to describe what CPU registers are available without GDB needing prior knowledge of the CPU. Protocol details can be found in the GDB documentation. Currently only ARM and ColdFire provide these descriptions, and only the basic core+fpu registers are described. Future extensions include banked registers, privileged registers, MMU state, etc. Other targets should not see any functional changes. Please test your favourite targets and let me know if I broke anything. Paul