From: Nathan Froyd <froydnj@codesourcery.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH][ppc] convert SPE logical instructions to TCG
Date: Tue, 14 Oct 2008 10:19:35 -0700 [thread overview]
Message-ID: <20081014171934.GL18389@codesourcery.com> (raw)
As the subject suggests. I was unsure of whether to use the cpu_T array
or just create new TCG locals; I opted for the latter approach, since
that approach seems a little more in spirit with how TCG is supposed to
be used, even if it's at odds with the rest of the PPC backend. If this
decision is a poor one, let me know and I can update the patch.
-Nathan
Index: target-ppc/op.c
===================================================================
--- target-ppc/op.c (revision 5485)
+++ target-ppc/op.c (working copy)
@@ -2513,54 +2513,6 @@
RETURN();
}
-void OPPROTO op_evand (void)
-{
- T0_64 &= T1_64;
- RETURN();
-}
-
-void OPPROTO op_evandc (void)
-{
- T0_64 &= ~T1_64;
- RETURN();
-}
-
-void OPPROTO op_evor (void)
-{
- T0_64 |= T1_64;
- RETURN();
-}
-
-void OPPROTO op_evxor (void)
-{
- T0_64 ^= T1_64;
- RETURN();
-}
-
-void OPPROTO op_eveqv (void)
-{
- T0_64 = ~(T0_64 ^ T1_64);
- RETURN();
-}
-
-void OPPROTO op_evnor (void)
-{
- T0_64 = ~(T0_64 | T1_64);
- RETURN();
-}
-
-void OPPROTO op_evorc (void)
-{
- T0_64 |= ~T1_64;
- RETURN();
-}
-
-void OPPROTO op_evnand (void)
-{
- T0_64 = ~(T0_64 & T1_64);
- RETURN();
-}
-
void OPPROTO op_evsrws (void)
{
do_evsrws();
Index: target-ppc/translate.c
===================================================================
--- target-ppc/translate.c (revision 5485)
+++ target-ppc/translate.c (working copy)
@@ -5453,14 +5453,139 @@
}
/* Logical */
-GEN_SPEOP_ARITH2(evand);
-GEN_SPEOP_ARITH2(evandc);
-GEN_SPEOP_ARITH2(evxor);
-GEN_SPEOP_ARITH2(evor);
-GEN_SPEOP_ARITH2(evnor);
-GEN_SPEOP_ARITH2(eveqv);
-GEN_SPEOP_ARITH2(evorc);
-GEN_SPEOP_ARITH2(evnand);
+static always_inline void gen_evand (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_and_i64(t0, t0, t1);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_evandc (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_not_i64(t1, t1);
+ tcg_gen_and_i64(t0, t0, t1);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_evxor (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_xor_i64(t0, t0, t1);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_evor (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_or_i64(t0, t0, t1);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_evnor (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_not_i64(t0, t0);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_eveqv (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_xor_i64(t0, t0, t1);
+ tcg_gen_not_i64(t0, t0);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_evorc (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_not_i64(t1, t1);
+ tcg_gen_or_i64(t0, t0, t1);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static always_inline void gen_evnand (DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ GEN_EXCP_NO_AP(ctx);
+ return;
+ }
+ TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);
+ gen_load_gpr64(t0, rA(ctx->opcode));
+ gen_load_gpr64(t1, rB(ctx->opcode));
+ tcg_gen_and_i64(t0, t0, t1);
+ tcg_gen_not_i64(t0, t0);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
GEN_SPEOP_ARITH2(evsrwu);
GEN_SPEOP_ARITH2(evsrws);
GEN_SPEOP_ARITH2(evslw);
next reply other threads:[~2008-10-14 17:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-14 17:19 Nathan Froyd [this message]
2008-10-14 17:33 ` [Qemu-devel] [PATCH][ppc] convert SPE logical instructions to TCG C.W. Betts
2008-10-14 17:33 ` C.W. Betts
2008-10-14 19:16 ` Aurelien Jarno
2008-10-15 2:09 ` Nathan Froyd
2008-10-15 9:32 ` Paul Brook
2008-10-15 17:00 ` Aurelien Jarno
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