From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KyjFd-0005Yr-JE for qemu-devel@nongnu.org; Sat, 08 Nov 2008 03:33:01 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KyjFc-0005Yf-1L for qemu-devel@nongnu.org; Sat, 08 Nov 2008 03:33:00 -0500 Received: from [199.232.76.173] (port=48065 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KyjFb-0005Yc-Vv for qemu-devel@nongnu.org; Sat, 08 Nov 2008 03:33:00 -0500 Received: from mx20.gnu.org ([199.232.41.8]:19400) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KyjFb-0006Xn-DH for qemu-devel@nongnu.org; Sat, 08 Nov 2008 03:32:59 -0500 Received: from hall.aurel32.net ([88.191.82.174]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KyjFa-0001W3-Nr for qemu-devel@nongnu.org; Sat, 08 Nov 2008 03:32:59 -0500 Date: Sat, 8 Nov 2008 09:32:57 +0100 From: Aurelien Jarno Message-ID: <20081108083257.GD9549@volta.aurel32.net> References: <20081108083118.GB9549@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20081108083118.GB9549@volta.aurel32.net> Subject: [Qemu-devel] [PATCH 02/11] target-mips: optimize gen_op_addr_add() (1/2) Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The user mode can be tested at translation time using ctx->hflags. This simplifies gen_op_addr_add(). Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 16 ++++++---------- 1 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index dcd8094..cbe8120 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -894,7 +894,7 @@ generate_exception (DisasContext *ctx, int excp) } /* Addresses computation */ -static inline void gen_op_addr_add (TCGv t0, TCGv t1) +static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1) { tcg_gen_add_tl(t0, t0, t1); @@ -902,17 +902,13 @@ static inline void gen_op_addr_add (TCGv t0, TCGv t1) /* For compatibility with 32-bit code, data reference in user mode with Status_UX = 0 should be casted to 32-bit and sign extended. See the MIPS64 PRA manual, section 4.10. */ - { + if ((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) { int l1 = gen_new_label(); - TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32); + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags)); - tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU); - tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1); tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status)); tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX)); tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1); - tcg_temp_free(r_tmp); tcg_gen_ext32s_i64(t0, t0); gen_set_label(l1); } @@ -1070,7 +1066,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, } else { gen_load_gpr(t0, base); tcg_gen_movi_tl(t1, offset); - gen_op_addr_add(t0, t1); + gen_op_addr_add(ctx, t0, t1); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -1235,7 +1231,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, gen_load_gpr(t0, base); tcg_gen_movi_tl(t1, offset); - gen_op_addr_add(t0, t1); + gen_op_addr_add(ctx, t0, t1); tcg_temp_free(t1); } /* Don't do NOP if destination is zero: we must perform the actual @@ -7369,7 +7365,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } else { gen_load_gpr(t0, base); gen_load_gpr(t1, index); - gen_op_addr_add(t0, t1); + gen_op_addr_add(ctx, t0, t1); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ -- 1.5.6.5 -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net