From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 10/11] target-mips: gen_compute_branch1()
Date: Sat, 8 Nov 2008 09:39:11 +0100 [thread overview]
Message-ID: <20081108083911.GL9549@volta.aurel32.net> (raw)
In-Reply-To: <20081108083118.GB9549@volta.aurel32.net>
Optimize code generation in gen_compute_branch1():
- Directly use I32 variables instead of converting values from _tl to
_i32 and back to _tl.
- Write the result directly to bcond instead of passing by a local
variable.
- Temp variables are valid up to and *including* the brcond instruction.
Use them instead of temp local variables.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/translate.c | 127 +++++++++++++++-------------------------------
1 files changed, 42 insertions(+), 85 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2970ae2..fdd7530 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5634,8 +5634,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
target_ulong btarget;
const char *opn = "cp1 cond branch";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
if (cc != 0)
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
@@ -5647,19 +5646,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1f";
@@ -5668,19 +5662,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1fl";
@@ -5689,18 +5678,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1t";
@@ -5709,42 +5694,32 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0x1 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x1 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1tl";
likely:
ctx->hflags |= MIPS_HFLAG_BL;
- tcg_gen_trunc_tl_i32(bcond, t0);
break;
case OPC_BC1FANY2:
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0x3 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x3 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any2f";
@@ -5753,18 +5728,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0x3 << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0x3 << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any2t";
@@ -5773,19 +5744,14 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_not_tl(t0, t0);
- tcg_gen_movi_tl(t1, 0xf << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0xf << cc);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any4f";
@@ -5794,37 +5760,28 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
int l1 = gen_new_label();
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- get_fp_cond(r_tmp1);
- tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_gen_movi_tl(t1, 0xf << cc);
- tcg_gen_and_tl(t0, t0, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
- tcg_gen_movi_tl(t0, 0);
+ get_fp_cond(t0);
+ tcg_gen_andi_i32(t0, t0, 0xf << cc);
+ tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
+ tcg_gen_movi_i32(bcond, 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_tl(t0, 1);
+ tcg_gen_movi_i32(bcond, 1);
gen_set_label(l2);
}
opn = "bc1any4t";
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
- tcg_gen_trunc_tl_i32(bcond, t0);
break;
default:
MIPS_INVAL(opn);
generate_exception (ctx, EXCP_RI);
- goto out;
+ return;
}
MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
ctx->hflags, btarget);
ctx->btarget = btarget;
-
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* Coprocessor 1 (FPU) */
--
1.5.6.5
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
next prev parent reply other threads:[~2008-11-08 8:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-11-08 8:31 [Qemu-devel] [PATCH 0/11] target-mips: optimizations Aurelien Jarno
2008-11-08 8:32 ` [Qemu-devel] [PATCH 01/11] target-mips: optimize gen_save_pc() Aurelien Jarno
2008-11-08 8:32 ` [Qemu-devel] [PATCH 02/11] target-mips: optimize gen_op_addr_add() (1/2) Aurelien Jarno
2008-11-08 8:33 ` [Qemu-devel] [PATCH 03/11] target-mips: optimize gen_op_addr_add() (2/2) Aurelien Jarno
2008-11-08 8:34 ` [Qemu-devel] [PATCH 04/11] target-mips: convert bitfield ops to TCG Aurelien Jarno
2008-11-08 12:57 ` Laurent Desnogues
2008-11-08 19:13 ` Aurelien Jarno
2008-11-08 8:34 ` [Qemu-devel] [PATCH 05/11] target-mips: convert bit shuffle " Aurelien Jarno
2008-11-08 8:35 ` [Qemu-devel] [PATCH 06/11] target-mips: optimize gen_arith()/gen_arith_imm() Aurelien Jarno
2008-11-08 8:37 ` [Qemu-devel] [PATCH 07/11] target-mips: optimize gen_muldiv() Aurelien Jarno
2008-11-08 8:37 ` [Qemu-devel] [PATCH 08/11] target-mips: optimize gen_farith() Aurelien Jarno
2008-11-08 8:38 ` [Qemu-devel] [PATCH 09/11] target-mips: optimize movc*() Aurelien Jarno
2008-11-08 8:39 ` Aurelien Jarno [this message]
2008-11-08 8:39 ` [Qemu-devel] [PATCH 11/11] target-mips: fix temporary variable freeing in op_ldst_##insn() Aurelien Jarno
-- strict thread matches above, loose matches on Subject: below --
2008-11-08 19:16 [Qemu-devel] [PATCH v2 0/11] target-mips: optimizations Aurelien Jarno
2008-11-08 19:21 ` [Qemu-devel] [PATCH 10/11] target-mips: gen_compute_branch1() Aurelien Jarno
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