From mboxrd@z Thu Jan 1 00:00:00 1970 From: Guillaume Thouvenin Subject: Re: [Patch 4/5] x86_emulator: add the assembler code for three operands Date: Wed, 26 Nov 2008 12:59:08 +0100 Message-ID: <20081126125908.1eb177d1@frecb000711> References: <20081103160036.499cb482@frecb000711> <20081103160504.3fa8c378@frecb000711> <4910222A.20201@redhat.com> <20081125085918.45bb29d2@frecb000711> <492C12B4.4050700@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: kvm To: Avi Kivity Return-path: Received: from ecfrec.frec.bull.fr ([129.183.4.8]:57290 "EHLO ecfrec.frec.bull.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751914AbYKZL7M (ORCPT ); Wed, 26 Nov 2008 06:59:12 -0500 In-Reply-To: <492C12B4.4050700@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On Tue, 25 Nov 2008 16:59:00 +0200 Avi Kivity wrote: > > > > +#define __emulate_2op_cl(_op,_src,_src2,_dst,_eflags,_wx,_wy) \ > > + do { \ > > + unsigned long _tmp; \ > > + \ > > + __asm__ __volatile__ ( \ > > + _PRE_EFLAGS("0", "5", "2") \ > > + "mov %4, %%rcx \n\t" \ > > + _op" %%cl,%3,%1; \n\t" \ > > + _POST_EFLAGS("0", "5", "2") \ > > + : "=m" (_eflags), "=m" ((_dst).val), \ > > + "=&r" (_tmp) \ > > + : _wy ((_src).val) , _wy ((_src2).val), "i" (EFLAGS_MASK) \ > > + : "%rcx" ); \ > > + } while (0) > > > > I tested the code and it seems to work. > > > > That's actually better and could be used for the other emulations. > Please disassemble x86_emulate.o and verify that there are three > different shld instructions, one for each register size. > I tried with the following code (it's nearly the same as above): + __asm__ __volatile__ ( \ + _PRE_EFLAGS("0", "5", "2") \ + "mov %4, %%rcx \n\t" \ + _op" %3,%1; \n\t" \ + _POST_EFLAGS("0", "5", "2") \ + : "=m" (_eflags), "+r" ((_dst).val), \ + "=&r" (_tmp) \ + : _x ((_src).val) , _y ((_src2).val), "i" (EFLAGS_MASK) \ + : "%rcx" ); \ When I disassemble x86_emulate.o I can see the following produced code: 4787: ... 4788: 41 8f 44 24 08 popq 0x8(%r12) 478d: 48 89 d1 mov %rdx,%rcx 4790: 48 0f a5 f0 shld %cl,%rsi,%rax 4794: 9c pushfq 4795: ... It's the only code with shld instruction. I don't see how you can have three different shld instructions here. I'm sure that I'm missing something here because for me, when we emulate the shld instruction, the code produced is the same. I mean that src.val and dst.val are always unsigned long and I don't see why register size are important here. In fact I don't understand why we need to use the switch ((_dst).bytes) for the other emulations. Guillaume