From: Ingo Molnar <mingo@elte.hu>
To: Joerg Roedel <joerg.roedel@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org
Subject: Re: [PATCH] x86: fix broken flushing in GART nofullflush path
Date: Tue, 2 Dec 2008 20:27:59 +0100 [thread overview]
Message-ID: <20081202192759.GD15342@elte.hu> (raw)
In-Reply-To: <1228245363-14909-1-git-send-email-joerg.roedel@amd.com>
* Joerg Roedel <joerg.roedel@amd.com> wrote:
> In the non-default nofullflush case the GART is only flushed when
> next_bit wraps around. But it can happen that an unmap operation unmaps
> memory which is behind the current next_bit location. If these addresses
> are reused it may result in stale GART IO/TLB entries. Fix this by
> setting the GART next_bit always behind an unmapped location.
>
> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
> ---
> arch/x86/kernel/pci-gart_64.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
applied to tip/x86/iommu, thanks Joerg!
a stale iotlb should not cause any problems in this particular GART case,
right? It might be a security leak in a security-domain enforcing iotlb
case, but the GART is a DMA bouncing helper in essence. Can you see any
failure mode of this bug?
Ingo
next prev parent reply other threads:[~2008-12-02 19:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-12-02 19:16 [PATCH] x86: fix broken flushing in GART nofullflush path Joerg Roedel
2008-12-02 19:27 ` Ingo Molnar [this message]
2008-12-02 20:24 ` Joerg Roedel
2008-12-03 9:02 ` Ingo Molnar
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