From mboxrd@z Thu Jan 1 00:00:00 1970 From: Guillaume Thouvenin Subject: Re: [Patch 4/5] x86_emulator: add the assembler code for three operands Date: Wed, 3 Dec 2008 16:00:10 +0100 Message-ID: <20081203160010.67416536@frecb000711> References: <20081103160036.499cb482@frecb000711> <20081103160504.3fa8c378@frecb000711> <4910222A.20201@redhat.com> <20081125085918.45bb29d2@frecb000711> <492C12B4.4050700@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: Avi Kivity To: kvm Return-path: Received: from ecfrec.frec.bull.fr ([129.183.4.8]:52020 "EHLO ecfrec.frec.bull.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751278AbYLCPAY (ORCPT ); Wed, 3 Dec 2008 10:00:24 -0500 In-Reply-To: <492C12B4.4050700@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On Tue, 25 Nov 2008 16:59:00 +0200 Avi Kivity wrote: > That's actually better and could be used for the other emulations. > Please disassemble x86_emulate.o and verify that there are three > different shld instructions, one for each register size. For generating the three shld instructions I need to do the following: +/* Instruction has three operands like shld */ +#define __emulate_2op_cl(_op,_shift, _src, _dst,_eflags,_suffix) \ + do { \ + unsigned long _tmp; \ + __asm__ __volatile__ ( \ + _PRE_EFLAGS("0", "5", "2") \ + _op _suffix" %4,%1 \n\t" \ + _POST_EFLAGS("0", "5", "2") \ + : "=m" (_eflags), "+r" (_dst), \ + "=&r" (_tmp) \ + : "c" (_shift) , "r" (_src), "i" (EFLAGS_MASK) \ + ); \ + } while (0) + +#define emulate_2op_cl(_op, _shift, _src, _dst, _eflags) \ + do { \ + switch ((_dst).bytes) { \ + case 2: { \ + unsigned short shift = (_shift).val; \ + unsigned short src = (_src).val; \ + unsigned short dst = (_dst).val; \ + __emulate_2op_cl(_op,shift, src,dst,_eflags,"w"); \ + break; \ + } \ + case 4: { \ + unsigned int shift = (_shift).val; \ + unsigned int src = (_src).val; \ + unsigned int dst = (_dst).val; \ + __emulate_2op_cl(_op,shift, src,dst,_eflags,"l"); \ + break; \ + } \ + case 8: { \ + unsigned long shift = (_shift).val; \ + unsigned long src = (_src).val; \ + unsigned long dst = (_dst).val; \ + ON64(__emulate_2op_cl(_op,shift, src,dst,_eflags,"q")); \ + break; \ + } \ + } \ + } while (0) + Otherwise the code for "case 4:" cannot be generated. I've got: Error: Incorrect register `%rax' used with `l' suffix Is it correct? If yes I will repost patches that emulate shld/shrd instructions. Guillaume