From: Guillaume Thouvenin <guillaume.thouvenin@ext.bull.net>
To: kvm <kvm@vger.kernel.org>
Cc: Guillaume Thouvenin <guillaume.thouvenin@ext.bull.net>,
Avi Kivity <avi@redhat.com>
Subject: [Patch 4/5] x86_emulator: add the assembler code for three operands
Date: Thu, 4 Dec 2008 14:29:00 +0100 [thread overview]
Message-ID: <20081204142900.1b9bd1f8@frecb000711> (raw)
In-Reply-To: <20081204142418.709d321d@frecb000711>
Add the assembler code for instruction with three operands and one
operand is stored in ECX register
Signed-off-by: Guillaume Thouvenin <guillaume.thouvenin@ext.bull.net>
---
arch/x86/kvm/x86_emulate.c | 39 +++++++++++++++++++++++++++++++++++++++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c
index 0c75306..9ae6d5b 100644
--- a/arch/x86/kvm/x86_emulate.c
+++ b/arch/x86/kvm/x86_emulate.c
@@ -431,6 +431,45 @@ static u32 group2_table[] = {
__emulate_2op_nobyte(_op, _src, _dst, _eflags, \
"w", "r", _LO32, "r", "", "r")
+/* Instruction has three operands and one operand is stored in ECX register */
+#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
+ do { \
+ unsigned long _tmp; \
+ _type _clv = (_cl).val; \
+ _type _srcv = (_src).val; \
+ _type _dstv = (_dst).val; \
+ \
+ __asm__ __volatile__ ( \
+ _PRE_EFLAGS("0", "5", "2") \
+ _op _suffix " %4,%1 \n" \
+ _POST_EFLAGS("0", "5", "2") \
+ : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
+ : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
+ ); \
+ \
+ (_cl).val = (unsigned long) _clv; \
+ (_src).val = (unsigned long) _srcv; \
+ (_dst).val = (unsigned long) _dstv; \
+ } while (0)
+
+#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
+ do { \
+ switch ((_dst).bytes) { \
+ case 2: \
+ __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
+ "w", unsigned short); \
+ break; \
+ case 4: \
+ __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
+ "l", unsigned int); \
+ break; \
+ case 8: \
+ ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
+ "q", unsigned long)); \
+ break; \
+ } \
+ } while (0)
+
#define __emulate_1op(_op, _dst, _eflags, _suffix) \
do { \
unsigned long _tmp; \
--
1.6.0.4.623.g171d7
next prev parent reply other threads:[~2008-12-04 13:29 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-12-04 13:24 [Patch 0/5] x86_emulator: emulate shld and shrd instructions Guillaume Thouvenin
2008-12-04 13:25 ` [Patch 1/5] x86_emulator: Extend the opcode descriptor Guillaume Thouvenin
2008-12-04 13:26 ` [Patch 2/5] x86_emulator: add Src2 decode set Guillaume Thouvenin
2008-12-04 13:27 ` [Patch 3/5] x86_emulator: add a new "implied 1" Src decode type Guillaume Thouvenin
2008-12-04 13:29 ` Guillaume Thouvenin [this message]
2008-12-04 13:30 ` [Patch 5/5] x86_emulator: add the emulation of shld and shrd instructions Guillaume Thouvenin
2008-12-05 17:16 ` [Patch 0/5] x86_emulator: emulate " Avi Kivity
-- strict thread matches above, loose matches on Subject: below --
2008-11-03 15:00 [RFC Patch 0/5] x86_emulator: emulate shld and shrd instruction Guillaume Thouvenin
2008-11-03 15:05 ` [Patch 4/5] x86_emulator: add the assembler code for three operands Guillaume Thouvenin
2008-11-04 10:21 ` Avi Kivity
2008-11-25 7:59 ` Guillaume Thouvenin
2008-11-25 14:59 ` Avi Kivity
2008-11-26 11:59 ` Guillaume Thouvenin
2008-11-26 12:50 ` Avi Kivity
2008-12-03 15:00 ` Guillaume Thouvenin
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