From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753154AbYLQOyu (ORCPT ); Wed, 17 Dec 2008 09:54:50 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751209AbYLQOyh (ORCPT ); Wed, 17 Dec 2008 09:54:37 -0500 Received: from one.firstfloor.org ([213.235.205.2]:38785 "EHLO one.firstfloor.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751346AbYLQOyg (ORCPT ); Wed, 17 Dec 2008 09:54:36 -0500 Date: Wed, 17 Dec 2008 16:06:47 +0100 From: Andi Kleen To: Nils Smeds Cc: Andi Kleen , Samuel Thibault , William Cohen , Ingo Molnar , linux-kernel@vger.kernel.org, Peter Zijlstra , "David S. Miller" , Robert Richter , Eric Dumazet , Stephane Eranian , Paul Mackerras , Peter Anvin , Thomas Gleixner , Andrew Morton , perfctr-devel@lists.sourceforge.net, Arjan van de Ven Subject: Re: [Perfctr-devel] [patch] Performance Counters for Linux, v4 Message-ID: <20081217150647.GE25779@one.firstfloor.org> References: <20081214212829.GA9435@elte.hu> <494807D2.3060808@redhat.com> <87prjr1scl.fsf@basil.nowhere.org> <20081217015601.GE5147@const.famille.thibault.fr> <20081217091845.GC25779@one.firstfloor.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > OK, now I see where I got the understanding of this thread. > PERF_COUNT_CACHE_REFERENCES did not refer to a PAPI event. My error. Ok that makes sense. > A suggested kernel/user API that obscures the underlying PMU hardware > counters instead of exposing it to user level code should be dropped as It doesn't really obscure it (although there are some doubts it can express many of the more powerful/complicated features of modern PMUs), but provides a set of generalized standard events in addition, plus a "raw mode". The current list of events as of v4 is: + PERF_COUNT_CYCLES = 0, + PERF_COUNT_INSTRUCTIONS = 1, + PERF_COUNT_CACHE_REFERENCES = 2, + PERF_COUNT_CACHE_MISSES = 3, + PERF_COUNT_BRANCH_INSTRUCTIONS = 4, + PERF_COUNT_BRANCH_MISSES = 5, I think cache_references/misses is not well defined enough to be useful. The Intel architectural perfmon (which is a standard set of event supported over a range of Intel x86 micro architectures) has similar events defined as hitting the LLC (last level cache). With that it makes some sense. -Andi -- ak@linux.intel.com