From mboxrd@z Thu Jan 1 00:00:00 1970 From: Qing He Subject: Re: [PATCH 0/6] MSI-INTx interrupt translation for HVM Date: Thu, 8 Jan 2009 22:52:00 +0800 Message-ID: <20090108145200.GA23614@ub-qhe2> References: <1231405609-23138-1-git-send-email-qing.he@intel.com> <20090108194312.C770.CB716985@necst.nec.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20090108194312.C770.CB716985@necst.nec.co.jp> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Shohei Fujiwara Cc: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org On Thu, 2009-01-08 at 18:44 +0800, Shohei Fujiwara wrote: > I have one question. > > MSI interrupt is edge-triggered, and INTx interrupt is level-triggered. > Guest OS handles translated interrupt as level-triggered, though physical > interrupt is edge-triggered. When two interrupts are raised during short > period, Guest OS might lose 2nd interrupt, I think. This problem is handled by a different EOI timing. As soon as the hypervisor receives an MSI, it issues the EOI ASAP, and the duration of the injected level-triggered IRQ and guest EOI are all handled by the virtual APICs. If a 2nd interrupt comes up at this time, the hypervisor can receive the EOI and this results in a pending IRQ in virtual APICs instead of lost. Generally, it's easy to "translate" an edged interrupt to a level one, but not the other way. Thanks, Qing > > What do you think? > > Thanks, > -- > Shohei Fujiwara >