From: Russell King <rmk+lkml@arm.linux.org.uk>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>,
linux-arch@vger.kernel.org, Atsushi Nemoto <anemo@mba.ocn.ne.jp>,
dan.j.williams@intel.com, linux-kernel@vger.kernel.org,
maciej.sosnowski@intel.com
Subject: Re: [PATCH] dmatest: flush and invalidate destination buffer before DMA
Date: Fri, 9 Jan 2009 22:27:21 +0000 [thread overview]
Message-ID: <20090109222721.GA3618@flint.arm.linux.org.uk> (raw)
In-Reply-To: <20090109111936.GB17948@linux-mips.org>
On Fri, Jan 09, 2009 at 11:19:36AM +0000, Ralf Baechle wrote:
> On Thu, Jan 08, 2009 at 09:36:03AM +0100, Haavard Skinnemoen wrote:
> > In the general case, however, I think MIPS has a bug: I've seen drivers
> > DMA to/from tiny buffers stored inside another struct. This is legal
> > because the driver can guarantee that the other fields in the struct
> > aren't accessed in the mean time, but any fields sharing a cacheline
> > with the buffer must be written back before the lines are invalidated.
>
> Depending on the implementation details, the use of such a struct might be
> relying on implementation-specific behaviour. This is what
> Documentation/DMA-API.txt has to say:
>
> [...]
> int
> dma_get_cache_alignment(void)
>
> Returns the processor cache alignment. This is the absolute minimum
> alignment *and* width that you must observe when either mapping
> memory or doing partial flushes.
>
> Notes: This API may return a number *larger* than the actual cache
> line, but it will guarantee that one or more cache lines fit exactly
> into the width returned by this call. It will also always be a power
> of two for easy alignment.
> [...]
>
> Since dma_get_cache_alignment() is a function not a constant its result
> can't be used in the definition of a struct unless possibly excessive
> padding is used.
>
> The debate has shown that we problably need BUG_ON() assertions in the
> DMA API implementations to catch this sort of dangerous use.
I really don't think that's a realistic option. You're asking for
every call to the DMA API to ensure that the buffer and length are
a multiple of the cache line size.
So, what happens if, eg, SPI wants to send a 16 byte buffer, and your
cache lines are 64 bytes? Does the SPI driver have to kmalloc a new
chunk of memory 64 bytes long and copy the data into that before
passing it into the DMA API?
If you start enforcing that kind of thing, I think the cache coherent
people will take violent exception and refuse to play such games - and
quite rightly so.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of:
next prev parent reply other threads:[~2009-01-09 22:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-12-26 15:31 [PATCH] dmatest: flush and invalidate destination buffer before DMA Atsushi Nemoto
2008-12-27 10:10 ` Haavard Skinnemoen
2008-12-28 17:53 ` Atsushi Nemoto
2009-01-05 18:31 ` Dan Williams
2009-01-06 1:14 ` Atsushi Nemoto
2009-01-06 1:29 ` Dan Williams
2009-01-06 2:06 ` Atsushi Nemoto
2009-01-08 4:43 ` Atsushi Nemoto
2009-01-08 8:36 ` Haavard Skinnemoen
2009-01-08 17:20 ` Dan Williams
2009-01-09 8:30 ` Atsushi Nemoto
2009-01-10 0:39 ` Dan Williams
2009-01-09 11:19 ` Ralf Baechle
2009-01-09 22:27 ` Russell King [this message]
2009-01-11 18:44 ` Ralf Baechle
2009-01-11 18:44 ` Ralf Baechle
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